Difference between revisions of "RETRO-EP4CE15"
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Revision as of 12:47, 9 August 2020
Contents
Features
- Purchased FPGA Card
- QMTECH EP4CE15 Board
- Altera Cyclone IV EP4CE15F23C8N FPGA
- Winbond W9825C6KH-6 4M X 4 Banks x 16 bits SDRAM
- 3 Switches
- 2 LEDs
- DC power jack
- Power supply
- Alternate FPGA Board
- QMTECH Altera Intel FPGA Core Board Cyclone V CycloneV 5CEFA2F23 SDRAM - Alternate FPGA card Cyclone V
- On-Board FPGA: 5CEFA2F23;
- On-Board FPGA external crystal frequency: 50MHz;
- 5CEFA2F23 has rich RAM resource up to 1,760Kb;
- 5CEFA2F23 has 25K logic cells;
- On-Board Micron MT25QL128A SPI Flash, 16M bytes for user configuration code;
- On-Board Winbond 32MB SDRAM, W9825G6KH-6;
- On-Board 3.3V power supply for FPGA by using MP2315 wide input range DC/DC;
- 5CEFA2F23 core board has two 64p, 2.54mm pitch headers for extending 108 user IOs. All 108 user IOs are precisely designed with length matching;
- 5CEFA2F23 core board has 3 user switches;
- 5CEFA2F23 core board has 2 user LEDs;
- 5CEFA2F23 core board has JTAG interface, by using 10p, 2.54mm pitch header;
- 5CEFA2F23 core board PCB size is: 6.7cm x 8.4cm;
- Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm;
- 1MB SRAM
- For banked use in CP/M
- VGA connector
- 6 bit video (2:2:2)
- PS/2 connector
- FTDI USB to serial converter
- Micro USB
- FT230XS FTDI chip
- Tx/Rx LEDs
- SD or SDHC Card
- 2x6 Header
- 50-pin I/O Connector
FPGA Resources
- 56 1Kx9 RAM blocks
FPGA Boards
EP4CE15 FPGA Resources
- Power LED - D4
- User LED - D5 - FPGA Pin E4
- KEY0 - SW1 - FPGA Pin W13
- KEY1 - SW2 - FPGA Pin Y13
- nCONFIG - SW3
- JP5 - 5V
EP4CE15 Card Mechanicals
5CEFA2F23 FPGA Resources
- Power LED - D4 (On when 5V is applied)
- User LED - LED_D5 - FPGA Pin_D17
- KEY0 - SW1 - FPGA Pin_AB13
- RESET_N- SW2 - FPGA PIN_V16
- nCONFIG - SW3 - FPGA PIN_A4
- JP5 - 5V
5CEFA2F23 Card Mechanicals
Connectors - Using EP4CE15 FPGA Card
J1 - I/O Connector (EP4CE15 FPGA Card pin numbers)
U8 - FPGA to RETRO-EP4CE15 card (EP4CE15 FPGA Card pin numbers)
U7 - FPGA to RETRO-EP4CE15 card (EP4CE15 FPGA Card pin numbers)
Connectors - Using 5CEFA2F23 FPGA Card
J1 - I/O Connector (5CEFA2F23 FPGA Card pin numbers)
U8 - FPGA to RETRO-EP4CE15 (5CEFA2F23 FPGA Card pin numbers) card
U7 - FPGA to RETRO-EP4CE15 card (5CEFA2F23 FPGA Card pin numbers)
Connector Mapping
U7
U8
Headers/Jumpers
H1 - Power
- Power from USB 5V
- Do not power from FPGA when this jumper is installed
H2 - I/O Power Source
- 1-2 = FPGA Power
- 2-3 = On-board Regulator
J3 - Header (EP4CE15 FPGA pin numbers)
- J8P55 = IO_B22
- J8P56 = IO_B21
- J8B57 = IO_N20
- J8P58 = IO_N19
- J8P59 = IO_M20
- J8P60 = IO_M19
J3 - Header (5CEFA2F23 FPGA Card pin numbers)
- J8P55 = IO_B22
- J8P56 = IO_B21
- J8B57 = IO_N20
- J8P58 = IO_N19
- J8P59 = IO_M20
- J8P60 = IO_M19
P2 - PS/2 Keyboard
- PS2DAT = PIN_R1
- PS2CLK = PIN_R2
P3 - USB-C
- FT230X FTDI USB to Serial
# Serial Port set_location_assignment PIN_B22 -to serSelect set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to serSelect set_location_assignment PIN_B10 -to txd1 set_location_assignment PIN_B13 -to rxd1 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rxd1 set_location_assignment PIN_A10 -to rts1
P4 - SD Card
VGA - Ideal Drive 2:2:2 Case
- FPGA has a 3.3V driver which can drive 8 mA
- Ideal case drive current
- 0.7V into 75 Ohms = 9.33 mA
- R-2R values
- Ideal resistor values are 417.9 ohms and 835.7 ohms
- Standard value 1% resistors
- 1% standard values are 422 (Mouser), 845 (Mouser) Ohms
- Get closest values
- 0V, 0.228V, 0.460V, 0.693V
- Voltage steps are:
- Current steps are:
Schematic
Programming the FPGA EEPROM
- File
- Convert Programming File
- Configuration Device = EPCQ64
- Mode = Active Serial
- Programming File Type: *.jic
- Advanced = Check both Disables...
- Select Flash Loader
- Add Device = Cyclone IV and EP4CE15
- Select SOF Data
- Select Add File and select the .sof file
- Generate
- In Tools, Programmer
- Mode: JTAG
- Add file and select the .jic file
- Select Program/Configure
- Takes a while to program
- Press button near VGA
Multicomp Builds
Checkout
Rev 2 Issues
- GND on wrong USB pin
- Was pin 4, s/b pin 5
- Cut etch J4-4 to via
- Add wire J4-5 to via
- FT230XS +3.3V out needs 10 uF cap (min)
- Added 47uF electrolytic cap between via GND and vusb (3.3V) on rear of board
Rev 1 Issues
- Wrong DB15HD footprint
- Change to right footprint in Rev 2
- USB-C too hard to hand solder
- Changing to USB-B Micro in Rev 2
- Add 5V header in Rev 2
Rev 1 Prototype
- VGA connector footprint problem
- Using the J1 connector to VGAX49 card
Signal | VGAX49 Pin | RETRO Pin | FPGA Pin |
---|---|---|---|
GND | J1-19 | J1-49 | N/A |
R4 | J1-1 | J1-47 | C21 |
R3 | J1-2 | J1-48 | C22 |
G5 | J1-6 | J1-45 | D21 |
G4 | J1-7 | J1-46 | D22 |
B4 | J1-12 | J1-43 | E21 |
B3 | J1-13 | J1-44 | E22 |
HS | J1-17 | J1-41 | F21 |
VS | J1-18 | J1-42 | F22 |
- Serial
Signal | RETRO Pin | FPGA Pin |
---|---|---|
GND | J1-50 | N/A |
SerTx | J1-39 | H21 |
SerRx | J1-40 | H22 |
SerCts | J1-37 | J21 |
SerRts | J1-38 | J22 |
Testing with R32V2020 and Multicomp
- VGA (on P1 to VGAX49 Card) works
- Mounted on CARRIER95TO49MM board
- PS/2 Keyboard connector on RETRO-EP4CE15 works
- Installed R1, R2 - 10K pull-ups
- R32V2020 - Land Boards 32-bit RISC CPU Works
- 40K SRAM, BASIC UK101 worked
- External SRAM works - Tested 40KB
- CP/M tested - Works with SD Card
- Running ZEXALL
- Wrong color Mini-DIN (keyboard s/b purple)
Pin List
set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE15F23C8 set_global_assignment -name TOP_LEVEL_ENTITY Microcomputer set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:55:48 OCTOBER 20, 2013" set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" # Clock and reset set_location_assignment PIN_T2 -to i_CLOCK_50 set_location_assignment PIN_W13 -to n_reset set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to n_reset # PS/2 set_location_assignment PIN_R1 -to ps2Clk set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ps2Clk set_location_assignment PIN_R2 -to ps2Data set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ps2Data # Serial set_location_assignment PIN_B22 -to serSelect set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to serSelect set_location_assignment PIN_A13 -to cts1 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to cts1 set_location_assignment PIN_A10 -to rts1 set_location_assignment PIN_B13 -to rxd1 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to rxd1 set_location_assignment PIN_B10 -to txd1 # Video set_location_assignment PIN_B15 -to videoR0 set_location_assignment PIN_A15 -to videoR1 set_location_assignment PIN_B16 -to videoG0 set_location_assignment PIN_A16 -to videoG1 set_location_assignment PIN_B17 -to videoB0 set_location_assignment PIN_A17 -to videoB1 set_location_assignment PIN_B18 -to hSync set_location_assignment PIN_A18 -to vSync # SRAM set_location_assignment PIN_F1 -to n_sRamCS set_location_assignment PIN_B4 -to n_sRamWE set_location_assignment PIN_J2 -to n_sRamOE set_location_assignment PIN_E1 -to sramData[0] set_location_assignment PIN_C1 -to sramData[1] set_location_assignment PIN_B1 -to sramData[2] set_location_assignment PIN_B3 -to sramData[3] set_location_assignment PIN_B2 -to sramData[4] set_location_assignment PIN_C2 -to sramData[5] set_location_assignment PIN_D2 -to sramData[6] set_location_assignment PIN_F2 -to sramData[7] set_location_assignment PIN_H1 -to sramAddress[0] set_location_assignment PIN_J1 -to sramAddress[1] set_location_assignment PIN_M1 -to sramAddress[2] set_location_assignment PIN_N1 -to sramAddress[3] set_location_assignment PIN_P1 -to sramAddress[4] set_location_assignment PIN_P2 -to sramAddress[5] set_location_assignment PIN_N2 -to sramAddress[6] set_location_assignment PIN_M2 -to sramAddress[7] set_location_assignment PIN_H2 -to sramAddress[8] set_location_assignment PIN_A3 -to sramAddress[9] set_location_assignment PIN_A4 -to sramAddress[10] set_location_assignment PIN_C3 -to sramAddress[11] set_location_assignment PIN_A5 -to sramAddress[12] set_location_assignment PIN_A6 -to sramAddress[13] set_location_assignment PIN_A7 -to sramAddress[14] set_location_assignment PIN_A8 -to sramAddress[15] set_location_assignment PIN_B7 -to sramAddress[16] set_location_assignment PIN_B6 -to sramAddress[17] set_location_assignment PIN_B5 -to sramAddress[18] # SDRAM set_location_assignment PIN_Y6 -to sdRamClk set_location_assignment PIN_W6 -to sdRamClkEn set_location_assignment PIN_AA4 -to n_sdRamCas set_location_assignment PIN_AA3 -to n_sdRamCe set_location_assignment PIN_AB3 -to n_sdRamRas set_location_assignment PIN_AB4 -to n_sdRamWe set_location_assignment PIN_V2 -to sdRamAddr[0] set_location_assignment PIN_V1 -to sdRamAddr[1] set_location_assignment PIN_U2 -to sdRamAddr[2] set_location_assignment PIN_U1 -to sdRamAddr[3] set_location_assignment PIN_V3 -to sdRamAddr[4] set_location_assignment PIN_V4 -to sdRamAddr[5] set_location_assignment PIN_Y2 -to sdRamAddr[6] set_location_assignment PIN_AA1 -to sdRamAddr[7] set_location_assignment PIN_Y3 -to sdRamAddr[8] set_location_assignment PIN_V5 -to sdRamAddr[9] set_location_assignment PIN_W1 -to sdRamAddr[10] set_location_assignment PIN_Y4 -to sdRamAddr[11] set_location_assignment PIN_V6 -to sdRamAddr[12] set_location_assignment PIN_Y1 -to sdRamAddr[13] set_location_assignment PIN_W2 -to sdRamAddr[14] set_location_assignment PIN_AA10 -to sdRamData[0] set_location_assignment PIN_AB9 -to sdRamData[1] set_location_assignment PIN_AA9 -to sdRamData[2] set_location_assignment PIN_AB8 -to sdRamData[3] set_location_assignment PIN_AA8 -to sdRamData[4] set_location_assignment PIN_AB7 -to sdRamData[5] set_location_assignment PIN_AA7 -to sdRamData[6] set_location_assignment PIN_AB5 -to sdRamData[7] set_location_assignment PIN_Y7 -to sdRamData[8] set_location_assignment PIN_W8 -to sdRamData[9] set_location_assignment PIN_Y8 -to sdRamData[10] set_location_assignment PIN_V9 -to sdRamData[11] set_location_assignment PIN_V10 -to sdRamData[12] set_location_assignment PIN_Y10 -to sdRamData[13] set_location_assignment PIN_W10 -to sdRamData[14] set_location_assignment PIN_V11 -to sdRamData[15] # set_location_assignment PIN_AB14 -to IO_PIN[3] set_location_assignment PIN_AA14 -to IO_PIN[4] set_location_assignment PIN_AB15 -to IO_PIN[5] set_location_assignment PIN_AA15 -to IO_PIN[6] set_location_assignment PIN_AB16 -to IO_PIN[7] set_location_assignment PIN_AA16 -to IO_PIN[8] set_location_assignment PIN_AB17 -to IO_PIN[9] set_location_assignment PIN_AA17 -to IO_PIN[10] set_location_assignment PIN_AB18 -to IO_PIN[11] set_location_assignment PIN_AA18 -to IO_PIN[12] set_location_assignment PIN_AB19 -to IO_PIN[13] set_location_assignment PIN_AA19 -to IO_PIN[14] set_location_assignment PIN_AB20 -to IO_PIN[15] set_location_assignment PIN_AA20 -to IO_PIN[16] set_location_assignment PIN_Y21 -to IO_PIN[17] set_location_assignment PIN_Y22 -to IO_PIN[18] set_location_assignment PIN_W21 -to IO_PIN[19] set_location_assignment PIN_W22 -to IO_PIN[20] set_location_assignment PIN_V21 -to IO_PIN[21] set_location_assignment PIN_V22 -to IO_PIN[22] set_location_assignment PIN_U21 -to IO_PIN[23] set_location_assignment PIN_U22 -to IO_PIN[24] set_location_assignment PIN_R21 -to IO_PIN[25] set_location_assignment PIN_R22 -to IO_PIN[26] set_location_assignment PIN_P21 -to IO_PIN[27] set_location_assignment PIN_P22 -to IO_PIN[28] set_location_assignment PIN_N21 -to IO_PIN[29] set_location_assignment PIN_C22 -to IO_PIN[48] set_location_assignment PIN_C21 -to IO_PIN[47] set_location_assignment PIN_D22 -to IO_PIN[46] set_location_assignment PIN_D21 -to IO_PIN[45] set_location_assignment PIN_E22 -to IO_PIN[44] set_location_assignment PIN_E21 -to IO_PIN[43] set_location_assignment PIN_F22 -to IO_PIN[42] set_location_assignment PIN_F21 -to IO_PIN[41] set_location_assignment PIN_H22 -to IO_PIN[40] set_location_assignment PIN_H21 -to IO_PIN[39] set_location_assignment PIN_J22 -to IO_PIN[38] set_location_assignment PIN_J21 -to IO_PIN[37] set_location_assignment PIN_K22 -to IO_PIN[36] set_location_assignment PIN_K21 -to IO_PIN[35] set_location_assignment PIN_L22 -to IO_PIN[34] set_location_assignment PIN_L21 -to IO_PIN[33] set_location_assignment PIN_M22 -to IO_PIN[32] set_location_assignment PIN_M21 -to IO_PIN[31]