R32V2020 Instruction Set

All opcodes are 8-bits
There are seven opcode classes
- The opcode class is encoded in the top three bits of the instruction
The specific opcode within the class is the next five bits

Opcode Classes

The opcode classes are:

System
ALU
Immediate
Load/Store
Peripheral
Stack
Flow Control

System Opcodes

NOP - NO Operation

Performs a no operation
Does not change Condition Codes
Does not change the Register File contents (other than advancing the PC)
May end up being used prior to conditional branches as the pipelined is developed
Syntax

nop

HCF - Halt and Catch Fire

Causes the PC to stay at the current address
Can only be cleared by a reset or power cycling of the target hardware
Syntax

hcf

ALU Operations

ADD - Add two registers

Add two registers and store in a third
The three registers can be any register (even the same register)
Sets the Condition Code Register bits
Can be used with r0 to set designation register to zero
- ex: add r8,r0,r0 ; sets r8 = 0
Syntax

  add r10,r9,r8
  ; adds r8+r9 and stores in r10

ADD Immediate - Add Immediate to register

Add register to immediate and store in a register
The two registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

  addi r10,r9,0x10  ; adds 0x10+r9 and stores in r10

SUBtract - Subtract two registers

Add two registers and store in a third
The three registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

	lix		r10,7
	lix		r9,4
	sub		r8,r9,r10  ; r8 = r10 - r9

Result is 3

SUBtract Immediate - Subtract immediate from register

Subtract immediate from a register and store in a register
The two registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

	lix		r10,7
	subi		r8,r9,0x4  ; r8 = r10 - 0x4

Result is 3

MULtiply - Multiply two registers

Multiplies two registers and store in a third
The three registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

  mul r10,r9,r8
  ; multiplies r8 * r9 and stores in r10

MULtiply Immediate - Multiply register by an immediate

Multiplies immediate times a register and store in a register
The two registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

  muli r9,r8,0x5
  ; multiplies r8 * 5 and stores in r9

CMP - CoMPare

Compares two registers but does not store the result
The two registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

  cmp r8,r9
; compares r8 and r9 and sets condition code register bits

CMPI - CoMPare register and immediate

Compares immediate to register but does not store the result
Sets the Condition Code Register bits
Syntax

  cmpi r8,0x22  ; compares r8 and 0x22 and sets condition code register bits

OR - OR registers

Logical OR of two registers and store in a third
The three registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

  or r10,r9,r8
  ; Logical bit-wise OR of r8 OR r9 and stores in r10

ORI - OR Immediate register to immediate

Logical OR of immediate and register and store in a register
The two registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

  ori r9,r8,0x20   ; Logical bit-wise OR of r8 OR 0x20 and stores in r9

AND - AND registers

Logical AND of two registers and store in a third
The three registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

  and r10,r9,r8
  ; Logical bit-wise AND of r8 AND r9 and stores in r10

ANDI - AND immediate and register

Logical AND of register and immediate and store in a register
The two registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

  ando r9,r8,x0fe  ; Logical bit-wise AND of r8 AND 0xFE and stores in r9

XOR - eXclusive-or Registers

Logical Exclusive-OR of two registers and store in a third
The three registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

  xor r10,r9,r8
  ; Logical bit-wise Exclusive-OR of r8 XOR r9 and stores in r10

XORI - eXclusive-or Register and immediate

Logical Exclusive-OR of two registers and store in a third
The three registers can be any register (even the same register)
Sets the Condition Code Register bits
Syntax

  xori r9,r9,0xFF  ; Logical bit-wise Exclusive-OR of r8 XOR 0xFF and stores in r9

SL1 - Shift Left by 1

Shift register Left by 1 bit
Sets the Condition Code Register bits
Syntax

  sl1 r9,r8
  ; shift r8 left by 1 bit and stores in r9

SL8 - Shift Left by 8 bits

Shift register Left by 8 bit
Sets the Condition Code Register bits
Syntax

  sl8 r9,r8
  ; shift r8 left by 8 bits and stores in r9

SR1 - Shift Right by 1

Shift register Right by 1 bit
Sets the Condition Code Register bits
Syntax

  sr1 r9,r8
  ; shift r8 right by 1 bit and stores in r9

SR8 - Shift Right by 8

Shift register Right by 8 bits
Sets the Condition Code Register bits
Syntax

  sr1 r9,r8
  ; shift r8 right by 8 bits and stores in r9

ROL1 - Rotate Left by 1

Rotate register Left by 1 bit
Sets the Condition Code Register bits
Syntax

  rol1 r9,r8
  ; rotates r8 left by 1 bit and stores in r8

ROR1 - Rotate Right by 1

Rotate register Right by 1 bit
Sets the Condition Code Register bits
Syntax

  ror1 r9,r8
  ; rotates r8 right by 1 bit and stores in r9

ASR - Arithmetic shift Right by 1

Shift register Right by 1 bit
Most significant bit is duplicated (allows for signed math)
Sets the Condition Code Register bits
Syntax

  asr r9,r8
  ; shift r8 right by 1 bit and stores in r9

ENS - ENdian Swap

Swaps the endian of a long register into a long register
- d[31..24] > d[7..0]
- d[23..16] > d[15..8]
- d[15..8] > d[23..16]
- d[7..0] > d[31..24]
Useful for taking byte data packed into the Data RAM and re-ordering it to write it out to a peripheral
Syntax

  ens r9,r8
  ; endian swap r8 and stores in r9

Immediate Operations

LIL - Load Immediate Lower

Takes the bottom 16-bits of the Instruction and puts it into the lower half of a register
- Does not affect the upper half of the register
Syntax

  lil  r8,0x1234
  lil  dataLabel.lower

LIU - Load Immediate Upper

Takes the bottom 16-bits of the Instruction and puts it into the upper half of a register
- Does not affect the lower half of the register
Syntax

  liu  r8,0x1234
  liu  dataLabel.upper

LIX - Load Immediate Extended

Takes the bottom 20-bits of the Instruction and puts it into the lower half of a register
Sign extends the most significant bit into the top 20-bits
Syntax

  lix  r8,0x12345  ; leaves r8 = 0x00012345

Load/Store Operations

Load from the Data Memory into a register
Store from a register into the Data Memory
DAR (Data Address Register) points to the Data Memory
Post increment forms add one, two or four to the DAR (for byte, short, long transfers)

LDB[P] - Load Data Byte

Load register from a Data space
Size is byte
[P] - increment the DAR after the operation
Syntax

  ldb  r8

SDB[P] - Store Data Byte

Store a register to the Data space
Size is byte
[P] - increment the DAR after the operation
Syntax

  sdb  r8

LDS[P] - Load Data Short

Load register from a Data space
Size is short (16-bits)
[P] - increment the DAR after the operation
Syntax

  lds  r8

SDS[P] - Store Data Short

Store a register to the Data space
Size is short (16-bits)
[P] - increment the DAR after the operation
Syntax

  sds  r8

LDL[P] - Load Data Long

Load register from a Data space
Size is long (32-bits)
[P] - increment the DAR after the operation
Syntax

  ldl  r8

SDL[P] - Store Data Long

Store a register to the Data space
Size is long (32-bits)
[P] - increment the DAR after the operation
Syntax

  sdl  r8

Peripheral Operations

Load from the Peripheral Space into a register
Store from a register into the Peripheral Space
PAR (Peripheral Address Register) points to the Peripheral Memory
Post increment forms add one, two or four to the DAR (for byte, short, long transfers)

LPB[P] - Load Peripheral Byte

Load a byte from a peripheral into a register
[P] - increment the DAR after the operation
Syntax

  lpb  r8

SPB[P] - Store Peripheral Byte

Store a register to a peripheral - byte sized
[P] - increment the DAR after the operation
Syntax

  spb  r8

LPS[P] - Load Peripheral Short

Load a short from a peripheral into a register
[P] - increment the DAR after the operation
Syntax

  lps  r8

SPS[P] - Store Peripheral Short

Store a register to a peripheral - short sized
[P] - increment the DAR after the operation
Syntax

  sps  r8

LPL[P] - Load Peripheral Long

Load a long from a peripheral into a register
[P] - increment the DAR after the operation
Syntax

  lpl  r8

SPL - Store Peripheral Long

Store a register to a peripheral - long sized
[P] - increment the DAR after the operation
Syntax

  spl  r8

Stack Operations

PSS - Push Stack

Push a register onto the stack
Stack grows up in addresses
Auto-increments the stack pointer after the push
Syntax

  pss  r8

PUS - Pull Stack

Pull a value from the stack
Pre-decrements the stack pointer
Syntax

  pus  r8

SSS - Store to Stack

Store a long register value to the address pointed to by the stack pointer
Doesn't auto-increment the stack pointer
Syntax

  sss  r8

LSS - Load from Stack

Load a long from the address pointed to be the stack pointer
Syntax

  lss  r8

Flow Control

BRA - Branch Always

Unconditionally branches to an address
- Address is a signed 24-bit relative branch value
Syntax

  bra  label

BEZ - Branch Equal to Zero

Conditionally branches to an address if the CCR Equal to Zero bit is set
Address is a signed 24-bit relative branch value
Syntax

  beq  label

BE1 - Branch Equal to One

Conditionally branches to an address if the CCR Equal to One value bit is set
Address is a signed 24-bit relative branch value
Syntax

  be1  label

BNZ - Branch if Not Zero

Conditionally branches to an address if the CCR Not Zero value bit is set
Address is a signed 24-bit relative branch value
Syntax

  bnz  label

BCC - Branch if carry is clear

Conditionally branches to an address if the CCR Carry Clear bit is set to 1
Address is a signed 24-bit relative branch value
Syntax

  bcc  label

BCS - Branch if carry is set

Conditionally branches to an address if the CCR Carry Set bit is set to 1
Address is a signed 24-bit relative branch value
Syntax

  bcs  label

BLT - Branch Less Than

Conditionally branches to an address if the CCR Less Than bit is set
Address is a signed 24-bit relative branch value
Syntax

  blt  label

BGT - Branch Greater Than

Conditionally branches to an address if the CCR Greater Than bit is set
Address is a signed 24-bit relative branch value
Syntax

  bgt  label

BEQ - Branch Equal

Conditionally branches to an address if the CCR Equal bit is set
Address is a signed 24-bit relative branch value
Syntax

  beq  label

BNE - Branch Not Equal

Conditionally branches to an address if the CCR Not Equal bit is set
Address is a signed 24-bit relative branch value
Syntax

  bne  label

BSR - Branch Subroutine

Branches to a subroutine address
Address is a signed 24-bit relative branch value
Syntax

  bsr  label

To return form the subroutine, execute:

  pus  r7

R32V2020 Instruction Set

Contents

R32V2020 Instruction Set

Opcode Classes

System Opcodes

NOP - NO Operation

HCF - Halt and Catch Fire

ALU Operations

ADD - Add two registers

ADD Immediate - Add Immediate to register

SUBtract - Subtract two registers

SUBtract Immediate - Subtract immediate from register

MULtiply - Multiply two registers

MULtiply Immediate - Multiply register by an immediate

CMP - CoMPare

CMPI - CoMPare register and immediate

OR - OR registers

ORI - OR Immediate register to immediate

AND - AND registers

ANDI - AND immediate and register

XOR - eXclusive-or Registers

XORI - eXclusive-or Register and immediate

SL1 - Shift Left by 1

SL8 - Shift Left by 8 bits

SR1 - Shift Right by 1

SR8 - Shift Right by 8

ROL1 - Rotate Left by 1

ROR1 - Rotate Right by 1

ASR - Arithmetic shift Right by 1

ENS - ENdian Swap

Immediate Operations

LIL - Load Immediate Lower

LIU - Load Immediate Upper

LIX - Load Immediate Extended

Load/Store Operations

LDB[P] - Load Data Byte

SDB[P] - Store Data Byte

LDS[P] - Load Data Short

SDS[P] - Store Data Short

LDL[P] - Load Data Long

SDL[P] - Store Data Long

Peripheral Operations

LPB[P] - Load Peripheral Byte

SPB[P] - Store Peripheral Byte

LPS[P] - Load Peripheral Short

SPS[P] - Store Peripheral Short

LPL[P] - Load Peripheral Long

SPL - Store Peripheral Long

Stack Operations

PSS - Push Stack

PUS - Pull Stack

SSS - Store to Stack

LSS - Load from Stack

Flow Control

BRA - Branch Always

BEZ - Branch Equal to Zero

BE1 - Branch Equal to One

BNZ - Branch if Not Zero

BCC - Branch if carry is clear

BCS - Branch if carry is set

BLT - Branch Less Than

BGT - Branch Greater Than

BEQ - Branch Equal

BNE - Branch Not Equal

BSR - Branch Subroutine

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