Difference between revisions of "Multicomp in a Box"

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 +
[[file:MultiCompInBox_P1982_cropped_720px.jpg]]
 +
 
== Features ==
 
== Features ==
  
* Multicomp - FPGA retrocomputers
+
* This is an FPGA card in a box with support hardware
** 6502
+
** Provides a standardized interface for many FPGA Retrocomputer builds
*** OSI BASIC
+
* [[RETRO-EP4CE15]] base board for FPGA
*** UK101 / OSI C1P
+
** [[QM Tech Cyclone V FPGA Board]]
** 6800
+
*** 5CEFA2F23 has 25K logic cells
*** MIKBUG
+
*** 5CEFA2F23 has rich RAM resource up to 1,760Kb
** 6809
+
** USB-Serial
*** BASIC
+
*** Serial UART connected to FPGA
*** Beal Crook Multiple OS
+
*** Used to power box
** Z80
+
** VGA
*** CP/M (various builds)
+
*** 2:2:2 R:G:B
* 68000
+
** PS/2 keyboard connector
** Teeside 2 compatible
+
* 16 GPIO pins on DB-25 female connector
 +
* Reset switch on front of box
 +
* SD card accessible from front of box
 +
** On-board SD card not used
 +
* 4 externally accessible switches on bottom of box
 +
* Built in USB Blaster
 +
** Panel mounted USB mini
 +
 
 +
== Retro-Computer Builds ==
 +
 
 +
Supports [https://github.com/douggilliland/MultiComp/wiki Multicomp] and other [[RetroComputers|Retro-computer builds]]
 +
 
 +
=== Multicomp Builds ===
  
== Enclosure ==
+
* 6502
 +
** [https://github.com/douggilliland/MultiComp/tree/TS2_V001/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/M6502_VGA OSI BASIC]
 +
** [https://github.com/douggilliland/MultiComp/tree/TS2_V001/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/UK101_Int_41K UK101 / Ohio Scientific (OSI) C1P]
 +
* 6809
 +
** [https://github.com/douggilliland/MultiComp/tree/TS2_V001/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/M6809_VGA_PS2_IntRAM(56K) BASIC]
 +
** [https://github.com/douggilliland/MultiComp/tree/TS2_V001/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/MultiComp_6809_by_Neal_C-2019-04-08 Neal Crook Multiple OS]
 +
* Z80
 +
** [https://github.com/douggilliland/MultiComp/tree/TS2_V001/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/Multicomp-MPM CP/M (various builds)]
  
* [https://www.amazon.com/gp/product/B07SW4RQBQ/ref=ppx_yo_dt_b_search_asin_title?ie=UTF8&psc=1 YaeCCC Rectangle Project Enclosure Case Electric Junction Box Blue 170mm x 130mm x 80mm / 6.4" x 4.3" x 2.7"]
+
=== Other Builds ===
  
[[FILE:YaeCCC_CASE.PNG]]
+
* 6800
 +
** [https://github.com/douggilliland/MultiComp/tree/TS2_V001/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/M6800_MIKBUG_60KB_Banked-1MB MIKBUG]
 +
* 68000
 +
** [https://github.com/douggilliland/Retro-Computers/wiki/Teeside-2-68000 Teeside 2 (TS2) compatible]
 +
*** [https://github.com/douggilliland/Retro-Computers/tree/7ce0358bcddc7edb204a87fba47e80a591d9d570/68000/ReferenceDesigns/TS2_JeffTranter/monitor/TSBUG2 TS2BUG ROM]
 +
*** [https://github.com/douggilliland/Retro-Computers/tree/master/68000/TS2_FPGA/Tutor TUTOR ROM]
 +
** [https://github.com/douggilliland/Retro-Computers/tree/master/68000/TG68_AMR/TG68_AMR_FPGA/SOC/fpga/QMTECH_CycloneV_MCInBox TG68_AMR]
 +
* IOP-16
 +
** Our custom I/O Processor
 +
** [https://github.com/douggilliland/IOP16/wiki IOP16 Wiki GitHub]
 +
** [[IOP16 16-bit I/O CPU Design]]
 +
* PDP-11
 +
** [https://github.com/douggilliland/Retro-Computers/wiki/PDP-11-45-in-Box PDP-11/45]
 +
** [https://github.com/douggilliland/Retro-Computers/wiki/PDP-11-70-in-Box PDP-11/70]
  
== Card Set ==
+
=== Card Set ===
  
 
* [[RETRO-EP4CE15]] FPGA Baseboard
 
* [[RETRO-EP4CE15]] FPGA Baseboard
Line 28: Line 62:
 
* [[SWLEDX8|Slide switches card]] - Using 4 slide switches
 
* [[SWLEDX8|Slide switches card]] - Using 4 slide switches
 
* [[DB25-02]] - DB-25
 
* [[DB25-02]] - DB-25
* [[PD01|Power Distribution card]]
+
* [[PD01|PD01 - Power Distribution card]]
 
* Reset switch
 
* Reset switch
 
** Mounted to front panel
 
** Mounted to front panel
 
** On FPGA Pin_N16 (J3-6)
 
** On FPGA Pin_N16 (J3-6)
* [https://www.ebay.com/sch/i.html?_odkw=usb+blaster&_sop=15&LH_BIN=1&LH_FS=1&_osacat=0&_from=R40&_trksid=p2045573.m570.l1311.R2.TR6.TRC1.A0.H1.TRS1&_nkw=usb+blaster+altera&_sacat=0 USB Blaster] - Remove from case - Opening in enclosure to access USB connector
+
* [https://www.ebay.com/sch/i.html?_odkw=usb+blaster&_sop=15&LH_BIN=1&LH_FS=1&_osacat=0&_from=R40&_trksid=p2045573.m570.l1311.R2.TR6.TRC1.A0.H1.TRS1&_nkw=usb+blaster+altera&_sacat=0 USB Blaster]
 +
** [https://www.ebay.com/itm/26525309873450cm Panel Female to Mount Type Mini USB 5Pin Male Extension Adapter Cable] - feed USB Blaster to back panel
  
=== QM Tech Cyclone V FPGA Board Features ===
+
==== QM Tech Cyclone V FPGA Board Features ====
  
 
* [[QM Tech Cyclone V FPGA Board]]
 
* [[QM Tech Cyclone V FPGA Board]]
Line 52: Line 87:
 
** 5CEFA2F23 core board PCB size is: 6.7cm x 8.4cm
 
** 5CEFA2F23 core board PCB size is: 6.7cm x 8.4cm
 
** Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm
 
** Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm
 +
 +
===== Cyclone V_FPGA Resources =====
 +
 +
[[File:5CEFA2_FEATURES.PNG]]
 +
 +
* 176 1Kx10 RAM blocks
 +
 +
* Power LED - D4 (On when 5V is applied)
 +
* User LED - LED_D5 - FPGA Pin_D17 (pull low to illuminate LED) (inside box)
 +
* KEY0 - SW1 - FPGA Pin_AB13 (inside box)
 +
* RESET_N- SW2 - FPGA PIN_V18 (inside box)
 +
* nCONFIG - SW3 - FPGA PIN_A4 (inside box)
 +
* JP5 - 5V
 +
* Clock - FPGA PIN_M9
 +
 +
=== Pin List (5CEFA2F23I7) ===
 +
 +
* SD card and reset pins are different since they are cabled to the Front Panel
 +
 +
{| class="wikitable"
 +
! To
 +
! Direction
 +
! Location
 +
! I/O Standard
 +
! Pull-Up
 +
|-
 +
| cts1
 +
| Input
 +
| PIN_B11
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| hSync
 +
| Output
 +
| PIN_A15
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| i_clk
 +
| Input
 +
| PIN_M9
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| i_key1
 +
| Input
 +
| PIN_AB13
 +
| 3.3-V LVTTL
 +
| on
 +
|-
 +
| i_n_reset
 +
| Input
 +
| PIN_N16
 +
| 3.3-V LVTTL
 +
| on
 +
|-
 +
| n_sRamCS
 +
| Output
 +
| PIN_E2
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| n_sRamOE
 +
| Output
 +
| PIN_L2
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| n_sRamWE
 +
| Output
 +
| PIN_D6
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| n_sdRamCas
 +
| Output
 +
| PIN_AA7
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| n_sdRamCe
 +
| Output
 +
| PIN_AB5
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| n_sdRamRas
 +
| Output
 +
| PIN_AB6
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| n_sdRamWe
 +
| Output
 +
| PIN_W9
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| o_UsrLed
 +
| Output
 +
| PIN_D17
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| ps2Clk
 +
| Bidir
 +
| PIN_AA2
 +
| 3.3-V LVTTL
 +
| on
 +
|-
 +
| ps2Data
 +
| Bidir
 +
| PIN_AA1
 +
| 3.3-V LVTTL
 +
| on
 +
|-
 +
| rts1
 +
| Output
 +
| PIN_F10
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| rxd1
 +
| Input
 +
| PIN_C11
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdCS
 +
| Output
 +
| PIN_M22
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdMISO
 +
| Input
 +
| PIN_L18
 +
| 3.3-V LVTTL
 +
| on
 +
|-
 +
| sdMOSI
 +
| Output
 +
| PIN_L22
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[0]
 +
| Output
 +
| PIN_P8
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[1]
 +
| Output
 +
| PIN_P7
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[2]
 +
| Output
 +
| PIN_N8
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[3]
 +
| Output
 +
| PIN_N6
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[4]
 +
| Output
 +
| PIN_U6
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[5]
 +
| Output
 +
| PIN_U7
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[6]
 +
| Output
 +
| PIN_V6
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[7]
 +
| Output
 +
| PIN_U8
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[8]
 +
| Output
 +
| PIN_T8
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[9]
 +
| Output
 +
| PIN_W8
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[10]
 +
| Output
 +
| PIN_R6
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[11]
 +
| Output
 +
| PIN_T9
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[12]
 +
| Output
 +
| PIN_Y9
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[13]
 +
| Output
 +
| PIN_T7
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamAddr[14]
 +
| Output
 +
| PIN_P9
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamClk
 +
| Output
 +
| PIN_AB11
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamClkEn
 +
| Output
 +
| PIN_V9
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[0]
 +
| Input
 +
| PIN_AA12
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[1]
 +
| Input
 +
| PIN_Y11
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[2]
 +
| Input
 +
| PIN_AA10
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[3]
 +
| Input
 +
| PIN_AB10
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[4]
 +
| Input
 +
| PIN_Y10
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[5]
 +
| Input
 +
| PIN_AA9
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[6]
 +
| Input
 +
| PIN_AB8
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[7]
 +
| Input
 +
| PIN_AA8
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[8]
 +
| Input
 +
| PIN_U10
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[9]
 +
| Input
 +
| PIN_T10
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[10]
 +
| Input
 +
| PIN_U11
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[11]
 +
| Input
 +
| PIN_R10
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[12]
 +
| Input
 +
| PIN_R11
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[13]
 +
| Input
 +
| PIN_U12
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[14]
 +
| Input
 +
| PIN_R12
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdRamData[15]
 +
| Input
 +
| PIN_P12
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sdSCLK
 +
| Output
 +
| PIN_L19
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| serSelect
 +
| Input
 +
| PIN_L17
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[0]
 +
| Output
 +
| PIN_G1
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[1]
 +
| Output
 +
| PIN_L1
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[2]
 +
| Output
 +
| PIN_N1
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[3]
 +
| Output
 +
| PIN_U1
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[4]
 +
| Output
 +
| PIN_Y3
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[5]
 +
| Output
 +
| PIN_W2
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[6]
 +
| Output
 +
| PIN_U2
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[7]
 +
| Output
 +
| PIN_N2
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[8]
 +
| Output
 +
| PIN_G2
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[9]
 +
| Output
 +
| PIN_E7
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[10]
 +
| Output
 +
| PIN_C6
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[11]
 +
| Output
 +
| PIN_D9
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[12]
 +
| Output
 +
| PIN_A5
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[13]
 +
| Output
 +
| PIN_B7
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[14]
 +
| Output
 +
| PIN_A8
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[15]
 +
| Output
 +
| PIN_A10
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[16]
 +
| Output
 +
| PIN_A7
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[17]
 +
| Output
 +
| PIN_B6
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[18]
 +
| Output
 +
| PIN_B5
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramAddress[19]
 +
| Output
 +
| PIN_E9
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramData[0]
 +
| Bidir
 +
| PIN_C1
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramData[1]
 +
| Bidir
 +
| PIN_G6
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramData[2]
 +
| Bidir
 +
| PIN_G8
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramData[3]
 +
| Bidir
 +
| PIN_F7
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramData[4]
 +
| Bidir
 +
| PIN_H8
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramData[5]
 +
| Bidir
 +
| PIN_H6
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramData[6]
 +
| Bidir
 +
| PIN_C2
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| sramData[7]
 +
| Bidir
 +
| PIN_D3
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| txd1
 +
| Output
 +
| PIN_G10
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| vSync
 +
| Output
 +
| PIN_A14
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| videoB0
 +
| Output
 +
| PIN_B13
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| videoB1
 +
| Output
 +
| PIN_A13
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| videoG0
 +
| Output
 +
| PIN_D13
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| videoG1
 +
| Output
 +
| PIN_C13
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| videoR0
 +
| Output
 +
| PIN_E12
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
| videoR1
 +
| Output
 +
| PIN_D12
 +
| 3.3-V LVTTL
 +
|
 +
|-
 +
|}
 +
 +
<pre>
 +
# -------------------------------------------------------------------------- #
 +
#
 +
# Copyright (C) 2018  Intel Corporation. All rights reserved.
 +
# Your use of Intel Corporation's design tools, logic functions
 +
# and other software and tools, and its AMPP partner logic
 +
# functions, and any output files from any of the foregoing
 +
# (including device programming or simulation files), and any
 +
# associated documentation or information are expressly subject
 +
# to the terms and conditions of the Intel Program License
 +
# Subscription Agreement, the Intel Quartus Prime License Agreement,
 +
# the Intel FPGA IP License Agreement, or other applicable license
 +
# agreement, including, without limitation, that your use is for
 +
# the sole purpose of programming logic devices manufactured by
 +
# Intel and sold by Intel or its authorized distributors.  Please
 +
# refer to the applicable agreement for further details.
 +
#
 +
# -------------------------------------------------------------------------- #
 +
#
 +
# Quartus Prime
 +
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
 +
# Date created = 07:21:26  July 04, 2020
 +
#
 +
# -------------------------------------------------------------------------- #
 +
#
 +
# Notes:
 +
#
 +
# 1) The default values for assignments are stored in the file:
 +
# TS2_68000_assignment_defaults.qdf
 +
#    If this file doesn't exist, see file:
 +
# assignment_defaults.qdf
 +
#
 +
# 2) Altera recommends that you do not modify this file. This
 +
#    file is updated automatically by the Quartus Prime software
 +
#    and any changes you make may be lost or overwritten.
 +
#
 +
# -------------------------------------------------------------------------- #
 +
 +
set_global_assignment -name FAMILY "Cyclone V"
 +
set_global_assignment -name DEVICE 5CEFA2F23I7
 +
set_global_assignment -name TOP_LEVEL_ENTITY TS2_68000_Top
 +
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 +
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:21:26  JULY 04, 2020"
 +
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
 +
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 +
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
 +
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
 +
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
 +
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (VHDL)"
 +
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
 +
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
 +
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 +
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 +
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 +
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 +
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 +
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
 +
set_global_assignment -name SMART_RECOMPILE ON
 +
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
 +
set_global_assignment -name ENABLE_SIGNALTAP OFF
 +
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
 +
set_global_assignment -name ENABLE_OCT_DONE OFF
 +
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
 +
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
 +
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
 +
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
 +
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
 +
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
 +
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
 +
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
 +
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
 +
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
 +
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
 +
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
 +
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
 +
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
 +
# Clock and reset
 +
set_location_assignment PIN_M9 -to i_CLOCK_50
 +
set_location_assignment PIN_N16 -to i_n_reset
 +
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n_reset
 +
# Serial
 +
set_location_assignment PIN_B11 -to i_cts1
 +
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_cts1
 +
set_location_assignment PIN_F10 -to o_rts1
 +
set_location_assignment PIN_C11 -to i_rxd1
 +
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_rxd1
 +
set_location_assignment PIN_G10 -to o_txd1
 +
set_location_assignment PIN_L17 -to i_serSelect
 +
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_serSelect
 +
# SRAM
 +
set_location_assignment PIN_E2 -to o_n_sRamCS
 +
set_location_assignment PIN_L2 -to o_n_sRamOE
 +
set_location_assignment PIN_D6 -to o_n_sRamWE
 +
set_location_assignment PIN_E9 -to o_sramAddress[19]
 +
set_location_assignment PIN_B5 -to o_sramAddress[18]
 +
set_location_assignment PIN_B6 -to o_sramAddress[17]
 +
set_location_assignment PIN_A7 -to o_sramAddress[16]
 +
set_location_assignment PIN_A10 -to o_sramAddress[15]
 +
set_location_assignment PIN_A8 -to o_sramAddress[14]
 +
set_location_assignment PIN_B7 -to o_sramAddress[13]
 +
set_location_assignment PIN_A5 -to o_sramAddress[12]
 +
set_location_assignment PIN_D9 -to o_sramAddress[11]
 +
set_location_assignment PIN_C6 -to o_sramAddress[10]
 +
set_location_assignment PIN_E7 -to o_sramAddress[9]
 +
set_location_assignment PIN_G2 -to o_sramAddress[8]
 +
set_location_assignment PIN_N2 -to o_sramAddress[7]
 +
set_location_assignment PIN_U2 -to o_sramAddress[6]
 +
set_location_assignment PIN_W2 -to o_sramAddress[5]
 +
set_location_assignment PIN_Y3 -to o_sramAddress[4]
 +
set_location_assignment PIN_U1 -to o_sramAddress[3]
 +
set_location_assignment PIN_N1 -to o_sramAddress[2]
 +
set_location_assignment PIN_L1 -to o_sramAddress[1]
 +
set_location_assignment PIN_G1 -to o_sramAddress[0]
 +
set_location_assignment PIN_C1 -to io_sramData[0]
 +
set_location_assignment PIN_G6 -to io_sramData[1]
 +
set_location_assignment PIN_G8 -to io_sramData[2]
 +
set_location_assignment PIN_F7 -to io_sramData[3]
 +
set_location_assignment PIN_H8 -to io_sramData[4]
 +
set_location_assignment PIN_H6 -to io_sramData[5]
 +
set_location_assignment PIN_C2 -to io_sramData[6]
 +
set_location_assignment PIN_D3 -to io_sramData[7]
 +
# External SD Card
 +
set_location_assignment PIN_M22 -to o_sdCS
 +
set_location_assignment PIN_L18 -to i_sdMISO
 +
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_sdMISO
 +
set_location_assignment PIN_L22 -to o_sdMOSI
 +
set_location_assignment PIN_L19 -to o_sdSCLK
 +
set_location_assignment PIN_D17 -to o_driveLED
 +
# Video
 +
set_location_assignment PIN_A15 -to o_hSync
 +
set_location_assignment PIN_A14 -to o_vSync
 +
set_location_assignment PIN_D12 -to o_videoR1
 +
set_location_assignment PIN_E12 -to o_videoR0
 +
set_location_assignment PIN_C13 -to o_videoG1
 +
set_location_assignment PIN_D13 -to o_videoG0
 +
set_location_assignment PIN_A13 -to o_videoB1
 +
set_location_assignment PIN_B13 -to o_videoB0
 +
# PS/2
 +
set_location_assignment PIN_AA2 -to io_ps2Clk
 +
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_ps2Clk
 +
set_location_assignment PIN_AA1 -to io_ps2Data
 +
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_ps2Data
 +
# 50-pin I/O Connector
 +
set_location_assignment PIN_AB15 -to IO_PIN[3]
 +
set_location_assignment PIN_AA15 -to IO_PIN[4]
 +
set_location_assignment PIN_Y14 -to IO_PIN[5]
 +
set_location_assignment PIN_Y15 -to IO_PIN[6]
 +
set_location_assignment PIN_AB17 -to IO_PIN[7]
 +
set_location_assignment PIN_AB18 -to IO_PIN[8]
 +
set_location_assignment PIN_Y16 -to IO_PIN[9]
 +
set_location_assignment PIN_Y17 -to IO_PIN[10]
 +
set_location_assignment PIN_AA17 -to IO_PIN[11]
 +
set_location_assignment PIN_AA18 -to IO_PIN[12]
 +
set_location_assignment PIN_AA19 -to IO_PIN[13]
 +
set_location_assignment PIN_AA20 -to IO_PIN[14]
 +
set_location_assignment PIN_Y19 -to IO_PIN[15]
 +
set_location_assignment PIN_Y20 -to IO_PIN[16]
 +
set_location_assignment PIN_AB20 -to IO_PIN[17]
 +
set_location_assignment PIN_AB21 -to IO_PIN[18]
 +
set_location_assignment PIN_AB22 -to IO_PIN[19]
 +
set_location_assignment PIN_AA22 -to IO_PIN[20]
 +
set_location_assignment PIN_Y22 -to IO_PIN[21]
 +
set_location_assignment PIN_W22 -to IO_PIN[22]
 +
set_location_assignment PIN_W21 -to IO_PIN[23]
 +
set_location_assignment PIN_Y21 -to IO_PIN[24]
 +
set_location_assignment PIN_V21 -to IO_PIN[25]
 +
set_location_assignment PIN_U22 -to IO_PIN[26]
 +
set_location_assignment PIN_W19 -to IO_PIN[27]
 +
set_location_assignment PIN_V20 -to IO_PIN[28]
 +
set_location_assignment PIN_U20 -to IO_PIN[29]
 +
set_location_assignment PIN_U21 -to IO_PIN[30]
 +
set_location_assignment PIN_T22 -to IO_PIN[31]
 +
set_location_assignment PIN_R22 -to IO_PIN[32]
 +
set_location_assignment PIN_R21 -to IO_PIN[33]
 +
set_location_assignment PIN_P22 -to IO_PIN[34]
 +
set_location_assignment PIN_T19 -to IO_PIN[35]
 +
set_location_assignment PIN_T20 -to IO_PIN[36]
 +
set_location_assignment PIN_P17 -to IO_PIN[37]
 +
set_location_assignment PIN_P16 -to IO_PIN[38]
 +
set_location_assignment PIN_N21 -to IO_PIN[39]
 +
set_location_assignment PIN_N20 -to IO_PIN[40]
 +
set_location_assignment PIN_M20 -to IO_PIN[41]
 +
set_location_assignment PIN_M21 -to IO_PIN[42]
 +
set_location_assignment PIN_N19 -to IO_PIN[43]
 +
set_location_assignment PIN_M18 -to IO_PIN[44]
 +
# SDRAM
 +
set_location_assignment PIN_AA7 -to o_sdram_cas
 +
set_location_assignment PIN_V9 -to o_sdram_cke
 +
set_location_assignment PIN_AB11 -to o_sdram_clk
 +
set_location_assignment PIN_AB5 -to o_sdram_cs
 +
set_location_assignment PIN_AB7 -to o_sdram_ldqm
 +
set_location_assignment PIN_V10 -to o_sdram_udqm
 +
set_location_assignment PIN_AB6 -to o_sdram_ras
 +
set_location_assignment PIN_W9 -to o_sdram_we
 +
set_location_assignment PIN_P9 -to o_sdram_ba[1]
 +
set_location_assignment PIN_T7 -to o_sdram_ba[0]
 +
set_location_assignment PIN_Y9 -to o_sdram_addr[12]
 +
set_location_assignment PIN_T9 -to o_sdram_addr[11]
 +
set_location_assignment PIN_R6 -to o_sdram_addr[10]
 +
set_location_assignment PIN_W8 -to o_sdram_addr[9]
 +
set_location_assignment PIN_T8 -to o_sdram_addr[8]
 +
set_location_assignment PIN_U8 -to o_sdram_addr[7]
 +
set_location_assignment PIN_V6 -to o_sdram_addr[6]
 +
set_location_assignment PIN_U7 -to o_sdram_addr[5]
 +
set_location_assignment PIN_U6 -to o_sdram_addr[4]
 +
set_location_assignment PIN_N6 -to o_sdram_addr[3]
 +
set_location_assignment PIN_N8 -to o_sdram_addr[2]
 +
set_location_assignment PIN_P7 -to o_sdram_addr[1]
 +
set_location_assignment PIN_P8 -to o_sdram_addr[0]
 +
set_location_assignment PIN_P12 -to io_sdram_data[15]
 +
set_location_assignment PIN_R12 -to io_sdram_data[14]
 +
set_location_assignment PIN_U12 -to io_sdram_data[13]
 +
set_location_assignment PIN_R11 -to io_sdram_data[12]
 +
set_location_assignment PIN_R10 -to io_sdram_data[11]
 +
set_location_assignment PIN_U11 -to io_sdram_data[10]
 +
set_location_assignment PIN_T10 -to io_sdram_data[9]
 +
set_location_assignment PIN_U10 -to io_sdram_data[8]
 +
set_location_assignment PIN_AA8 -to io_sdram_data[7]
 +
set_location_assignment PIN_AB8 -to io_sdram_data[6]
 +
set_location_assignment PIN_AA9 -to io_sdram_data[5]
 +
set_location_assignment PIN_Y10 -to io_sdram_data[4]
 +
set_location_assignment PIN_AB10 -to io_sdram_data[3]
 +
set_location_assignment PIN_AA10 -to io_sdram_data[2]
 +
set_location_assignment PIN_Y11 -to io_sdram_data[1]
 +
set_location_assignment PIN_AA12 -to io_sdram_data[0]
 +
#
 +
set_global_assignment -name VHDL_FILE TS2_68000_Top.vhd
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/UART/BaudRate6850.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/SDCARD/Older_SD_Controllers/sd_controller_NealC.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/COUNTER/n-bit-gray-counter.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/Debounce/LongDebounce/debounce.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/SBCTextDisplayRGB.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/SansBoldRomReduced.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/SansBoldRom.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/DisplayRam2K.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/DisplayRam1K.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/CGABoldRomReduced.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/CGABoldRom.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/UART/bufferedUART.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/CPU/M68000/TG68K_2013/TG68KdotC_Kernel.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/CPU/M68000/TG68K_2013/TG68K_Pack.vhd"
 +
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/CPU/M68000/TG68K_2013/TG68K_ALU.vhd"
 +
set_global_assignment -name VHDL_FILE Components/RAM_16Kx16.vhd
 +
set_global_assignment -name VHDL_FILE Components/RAM_4Kx16.vhd
 +
set_global_assignment -name QIP_FILE Components/Monitor_68K_ROM.qip
 +
set_global_assignment -name QIP_FILE Components/RAM_8Kx16.qip
 +
set_global_assignment -name QIP_FILE "../../MultiComp (VHDL Template)/Components/RAM_Internal/RAM_64KX16.qip"
 +
set_global_assignment -name QIP_FILE RAM_32Kx16.qip
 +
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 +
</pre>
  
 
== Power ==
 
== Power ==
  
 
* 5V Power comes from the USB
 
* 5V Power comes from the USB
* 3.3V regulator on the [[RETRO-EP4CE15]] Card
+
* 3.3V regulator on the [[RETRO-EP4CE15]] Card installed
 
** H2 pins 2-3 shorted on the [[RETRO-EP4CE15]] card
 
** H2 pins 2-3 shorted on the [[RETRO-EP4CE15]] card
** Set to route 3.3V to the I/O connector
+
** Routes 3.3V from the 3.3V regulator to the J1 I/O connector
 +
* [[PD01|Power Distribution card]]
 +
** Gets 3.3V and GND from I1 on [[RETRO-EP4CE15]] card
 +
*** 2 sets of wires
 +
** Distributes 3.3V and GND to SD and DB-25 cards
 +
 
 +
== Connectors ==
 +
 
 +
=== P2 - PS/2 Keyboard ===
 +
 
 +
* Not every PS/2 keyboard works at 3.3V but many do
 +
 
 +
[[File:PS2_Mapping.PNG]]
 +
 
 +
* PS2DAT = U7-8 = PIN_AA1
 +
* PS2CLK = U7-8 = PIN_AA2
 +
 
 +
=== VGA ===
 +
 
 +
[[file:J7_VGA.PNG]]
 +
 
 +
[[file:DB15HD_VGA.PNG]]
 +
 
 +
=== Serial ===
 +
 
 +
* USB B (full size)
 +
 
 +
[[file:RETROEP4-CE15_FTDI.PNG]]
 +
 
 +
[[file:RETROEP4-CE15_J7_SERIAL.PNG]]
 +
 
 +
=== SRAM ===
 +
 
 +
[[file:J7_SRAM.PNG]]
  
 
== Cabling ==
 
== Cabling ==
 +
 +
=== Slide Switches/Reset Pushbutton ===
 +
 +
* Slide switches are on the bottom of the box
 +
 +
[[file:MultiCompInBox_P1992_cropped_720px.jpg]]
 +
 +
[[file:RETROEP4-CE15_J3.PNG]]
 +
 +
* Pin assignments
 +
** PIN_L17 - Slide Switch 1 (top switch)
 +
** PIN_K17 - Slide Switch 2
 +
** PIN_K22 - Slide Switch 3
 +
** PIN_K21 - Slide Switch 4 (bottom switch)
 +
* Reset switch is on the front of the boz
 +
** PIN_N16 - Reset Switch
  
 
=== SD Card ===
 
=== SD Card ===
  
* [[SD_CARD_X49|SD Card]]
+
* [[SD_CARD_X49|External SD Card]]
 
* Install J3 on SD Card
 
* Install J3 on SD Card
 
** Runs card off 3.3V
 
** Runs card off 3.3V
 +
** NO5V jumper installed
  
 
{| class="wikitable"
 
{| class="wikitable"
Line 87: Line 996:
 
| GRY
 
| GRY
 
| 3
 
| 3
| L19
+
| PIN_L19
 
| OUT
 
| OUT
 
|-
 
|-
Line 94: Line 1,003:
 
| BLU
 
| BLU
 
| 2
 
| 2
| L18
+
| PIN_L18
 
| IN
 
| IN
 
|-
 
|-
Line 101: Line 1,010:
 
| WHT
 
| WHT
 
| 4
 
| 4
| L22
+
| PIN_L22
 
| OUT
 
| OUT
 
|-
 
|-
Line 108: Line 1,017:
 
| VIO
 
| VIO
 
| 5
 
| 5
| M22
+
| PIN_M22
 
| OUT
 
| OUT
 
|-
 
|-
Line 120: Line 1,029:
 
|}
 
|}
  
=== DB-25 ===
+
=== DB-25 Female ===
  
[[file:DB25-02_3D.png]]
+
[[file:DB25-02.PNG]]
  
[[file:DB25-02_SCHEMATIC.PNG]]
+
[[file:DB25Female-02_SCHEMATIC.PNG]]
  
 
* [[DB25-02]]
 
* [[DB25-02]]
 +
 +
[[file:DB25F_PINS.gif]]
 +
 +
==== DB-25 Cabling / Pin assignment ====
 +
 +
* gpio2/gpio3 are from IOP-16 design
 +
 +
{| class="wikitable"
 +
! DB25
 +
! P1(DB25F)
 +
! J1
 +
! Signal
 +
! FPGA
 +
!
 +
! DB25
 +
! P1(DB25F)
 +
! J1
 +
! Signal
 +
! FPGA
 +
|-
 +
| 1
 +
| 25
 +
|
 +
|
 +
|
 +
|
 +
|
 +
| 26
 +
|
 +
| NC
 +
|
 +
|-
 +
| 2
 +
| 23
 +
|
 +
| GND
 +
|
 +
|
 +
| 14
 +
| 24
 +
|
 +
| GND
 +
|
 +
|-
 +
| 3
 +
| 21
 +
| 44
 +
| gpio3[7]
 +
| PIN_M18
 +
|
 +
| 15
 +
| 22
 +
| 43
 +
| gpio3[6]
 +
| PIN_N19
 +
|-
 +
| 4
 +
| 19
 +
| 42
 +
| gpio3[5]
 +
| PIN_M21
 +
|
 +
| 16
 +
| 20
 +
| 41
 +
| gpio3[4]
 +
| PIN_M20
 +
|-
 +
| 5
 +
| 17
 +
| 40
 +
| gpio3[3]
 +
| PIN_N20
 +
|
 +
| 17
 +
| 18
 +
| 39
 +
| gpio3[2]
 +
| PIN_N21
 +
|-
 +
| 6
 +
| 15
 +
| 38
 +
| gpio3[1]
 +
| PIN_P16
 +
|
 +
| 18
 +
| 16
 +
| 37
 +
| gpio3[0]
 +
| PIN_P17
 +
|-
 +
| 7
 +
| 13
 +
| 36
 +
| gpio2[7]
 +
| PIN_T20
 +
|
 +
| 19
 +
| 14
 +
| 35
 +
| gpio2[6]
 +
| PIN_T19
 +
|-
 +
| 8
 +
| 11
 +
| 34
 +
| gpio2[5]
 +
| PIN_P22
 +
|
 +
| 20
 +
| 12
 +
| 33
 +
| gpio2[4]
 +
| PIN_R21
 +
|-
 +
| 9
 +
| 9
 +
| 32
 +
| gpio2[3]
 +
| PIN_R22
 +
|
 +
| 21
 +
| 10
 +
| 31
 +
| gpio2[2]
 +
| PIN_T22
 +
|-
 +
| 10
 +
| 7
 +
| 30
 +
| gpio2[1]
 +
| PIN_U21
 +
|
 +
| 22
 +
| 8
 +
| 29
 +
| gpio2[0]
 +
| PIN_U20
 +
|-
 +
| 11
 +
| 5
 +
|
 +
|
 +
|
 +
|
 +
| 23
 +
| 6
 +
|
 +
|
 +
|
 +
|-
 +
| 12
 +
| 3
 +
|
 +
|
 +
|
 +
|
 +
| 24
 +
| 4
 +
|
 +
|
 +
|
 +
|-
 +
| 13
 +
| 1
 +
|
 +
| +3.3V
 +
|
 +
|
 +
| 25
 +
| 2
 +
|
 +
| +3.3V
 +
|
 +
|-
 +
|}
 +
 +
== Programming the FPGA EEPROM ==
 +
 +
* File
 +
* Convert Programming File
 +
* Configuration Device = EPCQ64
 +
* Mode = Active Serial
 +
* Programming File Type: *.jic
 +
* Advanced = Check both Disables...
 +
* Select Flash Loader
 +
* Add Device = Cyclone V and 5CEFA2
 +
* Select SOF Data
 +
* Select Add File and select the .sof file
 +
* Generate
 +
* In Tools, Programmer
 +
* Mode: JTAG
 +
* Add file and select the .jic file
 +
* Select Program/Configure
 +
* Takes a while to program
 +
* Press button near VGA
 +
 +
== Front Panel I/O Demo Video ==
 +
 +
* [https://github.com/douggilliland/IOP16/tree/main/Higher_Level_Examples/TestIOP16_Max_5CEFA2 FPGA Files]
 +
* [https://github.com/douggilliland/IOP16/tree/main/IOP16_Code/IOP16_Menu Menu driven demonstration program tests peripherals]
 +
 +
<video type="youtube">0M8n1_wLdEc</video>
 +
 +
[[file:IOP-16_LEDs_P18125_720px.jpg]]
 +
 +
=== USB Panel Mount Connector ===
 +
 +
* USB Blaster embedded in the enclosure
 +
* USB Mini connector
 +
 +
[[FILE:USB_BLASTER_JACK.PNG]]
 +
 +
* USB-B Mini male/female cable to extend connection from the USB Blaster
 +
* [https://www.ebay.com/itm/265253098734 50cm Panel Female to Mount Type Mini USB 5Pin Male Extension Adapter Cable EBay listing]
 +
 +
[[file:USB_Extender_Cable.jpg]]
 +
 +
== Build Photos ==
 +
 +
* White-On-Clear P-Touch labels were used to mark front/rear panels
 +
* Rear viewL USB Blaster, VGA, USB-B, PS/2 Keyboard
 +
 +
[[file:MultiCompInBox_P1983_cropped_720px.jpg]]
 +
 +
* Top view: FPGA, SD Card, PD01 Power Distribution Card, USB Blaster, internal cabling
 +
 +
[[file:MultiCompInBox_P1985_cropped_720px.jpg]]
 +
 +
* USB Blaster attached to inside of rear panel using with Double Stick Tape
 +
 +
[[file:MultiCompInBox_P1986_720px.jpg]]
 +
 +
* Right inside of box: SD Card, Reset switch, PD01 Power Distribution card
 +
 +
[[file:MultiCompInBox_P1987_cropped_720pxV.jpg]]
 +
 +
* DB-25 connector card (not shown in enclosure)
 +
 +
[[file:MultiCompInBox_P1991_cropped.jpg]]
 +
 +
* Selection Switch on the bottom of the box
 +
* 4 switches
 +
 +
[[file:MultiCompInBox_P1992_cropped_720px.jpg]]
 +
 +
=== Enclosure ===
 +
 +
* [https://www.amazon.com/gp/product/B07SW4RQBQ/ref=ppx_yo_dt_b_search_asin_title?ie=UTF8&psc=1 YaeCCC Rectangle Project Enclosure Case Electric Junction Box Blue 170mm x 130mm x 80mm / 6.4" x 4.3" x 2.7"]
 +
 +
[[FILE:YaeCCC_CASE.PNG]]
  
 
== GitHub Repository ==
 
== GitHub Repository ==
Line 137: Line 1,298:
 
** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/MultiComp_6809_by_Neal_C-2019-04-08 MultiComp_6809_by_Neal_C-2019-04-08]
 
** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/MultiComp_6809_by_Neal_C-2019-04-08 MultiComp_6809_by_Neal_C-2019-04-08]
 
** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/Multicomp-MPM Multicomp-MPM]
 
** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/Multicomp-MPM Multicomp-MPM]
** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/TS2_68000 TS2_68000]
 
 
** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/UK101_41K UK101_41K]
 
** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/UK101_41K UK101_41K]
 
** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/UK101_Int_41K UK101_Int_41K]
 
** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/UK101_Int_41K UK101_Int_41K]
 +
** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15_Cyclone_V_InBox/TS2_68000 TS2_68000]
 +
** [https://github.com/douggilliland/Retro-Computers/tree/master/68000/TG68_AMR/TG68_AMR_FPGA/SOC/fpga/QMTECH_CycloneV_MCInBox TG68_AMR]
 +
** [https://github.com/douggilliland/IOP16/tree/main/Higher_Level_Examples/TestIOP16_InABox IOP-16]
 +
** [https://github.com/douggilliland/Retro-Computers/tree/master/PDP-11/PDP2011/PDP_11_45_InBox PDP-11/45 In a Box]
 +
** [https://github.com/douggilliland/Retro-Computers/tree/master/PDP-11/PDP2011/PDP_11_70_InBox PDP-11/70 In a Box]

Latest revision as of 20:45, 9 May 2022

MultiCompInBox P1982 cropped 720px.jpg

Features

  • This is an FPGA card in a box with support hardware
    • Provides a standardized interface for many FPGA Retrocomputer builds
  • RETRO-EP4CE15 base board for FPGA
    • QM Tech Cyclone V FPGA Board
      • 5CEFA2F23 has 25K logic cells
      • 5CEFA2F23 has rich RAM resource up to 1,760Kb
    • USB-Serial
      • Serial UART connected to FPGA
      • Used to power box
    • VGA
      • 2:2:2 R:G:B
    • PS/2 keyboard connector
  • 16 GPIO pins on DB-25 female connector
  • Reset switch on front of box
  • SD card accessible from front of box
    • On-board SD card not used
  • 4 externally accessible switches on bottom of box
  • Built in USB Blaster
    • Panel mounted USB mini

Retro-Computer Builds

Supports Multicomp and other Retro-computer builds

Multicomp Builds

Other Builds

Card Set

QM Tech Cyclone V FPGA Board Features

  • QM Tech Cyclone V FPGA Board
  • QMTECH Altera Intel FPGA Core Board Cyclone V CycloneV 5CEFA2F23 SDRAM
    • QMTECH GitHub page
    • On-Board FPGA: 5CEFA2F23I7N
    • On-Board FPGA external crystal frequency: 50MHz
    • 5CEFA2F23 has rich RAM resource up to 1,760Kb
    • 5CEFA2F23 has 25K logic cells
    • On-Board Micron MT25QL128A SPI Flash, 16M bytes for user configuration code
    • On-Board Winbond 32MB SDRAM, W9825G6KH-6
    • On-Board 3.3V power supply for FPGA by using MP2315 wide input range DC/DC
    • 5CEFA2F23 core board has two 64p, 2.54mm pitch headers for extending 108 user IOs. All 108 user IOs are precisely designed with length matching
    • 5CEFA2F23 core board has 3 user switches
    • 5CEFA2F23 core board has 2 user LEDs
    • 5CEFA2F23 core board has JTAG interface, by using 10p, 2.54mm pitch header
    • 5CEFA2F23 core board PCB size is: 6.7cm x 8.4cm
    • Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm
Cyclone V_FPGA Resources

5CEFA2 FEATURES.PNG

  • 176 1Kx10 RAM blocks
  • Power LED - D4 (On when 5V is applied)
  • User LED - LED_D5 - FPGA Pin_D17 (pull low to illuminate LED) (inside box)
  • KEY0 - SW1 - FPGA Pin_AB13 (inside box)
  • RESET_N- SW2 - FPGA PIN_V18 (inside box)
  • nCONFIG - SW3 - FPGA PIN_A4 (inside box)
  • JP5 - 5V
  • Clock - FPGA PIN_M9

Pin List (5CEFA2F23I7)

  • SD card and reset pins are different since they are cabled to the Front Panel
To Direction Location I/O Standard Pull-Up
cts1 Input PIN_B11 3.3-V LVTTL
hSync Output PIN_A15 3.3-V LVTTL
i_clk Input PIN_M9 3.3-V LVTTL
i_key1 Input PIN_AB13 3.3-V LVTTL on
i_n_reset Input PIN_N16 3.3-V LVTTL on
n_sRamCS Output PIN_E2 3.3-V LVTTL
n_sRamOE Output PIN_L2 3.3-V LVTTL
n_sRamWE Output PIN_D6 3.3-V LVTTL
n_sdRamCas Output PIN_AA7 3.3-V LVTTL
n_sdRamCe Output PIN_AB5 3.3-V LVTTL
n_sdRamRas Output PIN_AB6 3.3-V LVTTL
n_sdRamWe Output PIN_W9 3.3-V LVTTL
o_UsrLed Output PIN_D17 3.3-V LVTTL
ps2Clk Bidir PIN_AA2 3.3-V LVTTL on
ps2Data Bidir PIN_AA1 3.3-V LVTTL on
rts1 Output PIN_F10 3.3-V LVTTL
rxd1 Input PIN_C11 3.3-V LVTTL
sdCS Output PIN_M22 3.3-V LVTTL
sdMISO Input PIN_L18 3.3-V LVTTL on
sdMOSI Output PIN_L22 3.3-V LVTTL
sdRamAddr[0] Output PIN_P8 3.3-V LVTTL
sdRamAddr[1] Output PIN_P7 3.3-V LVTTL
sdRamAddr[2] Output PIN_N8 3.3-V LVTTL
sdRamAddr[3] Output PIN_N6 3.3-V LVTTL
sdRamAddr[4] Output PIN_U6 3.3-V LVTTL
sdRamAddr[5] Output PIN_U7 3.3-V LVTTL
sdRamAddr[6] Output PIN_V6 3.3-V LVTTL
sdRamAddr[7] Output PIN_U8 3.3-V LVTTL
sdRamAddr[8] Output PIN_T8 3.3-V LVTTL
sdRamAddr[9] Output PIN_W8 3.3-V LVTTL
sdRamAddr[10] Output PIN_R6 3.3-V LVTTL
sdRamAddr[11] Output PIN_T9 3.3-V LVTTL
sdRamAddr[12] Output PIN_Y9 3.3-V LVTTL
sdRamAddr[13] Output PIN_T7 3.3-V LVTTL
sdRamAddr[14] Output PIN_P9 3.3-V LVTTL
sdRamClk Output PIN_AB11 3.3-V LVTTL
sdRamClkEn Output PIN_V9 3.3-V LVTTL
sdRamData[0] Input PIN_AA12 3.3-V LVTTL
sdRamData[1] Input PIN_Y11 3.3-V LVTTL
sdRamData[2] Input PIN_AA10 3.3-V LVTTL
sdRamData[3] Input PIN_AB10 3.3-V LVTTL
sdRamData[4] Input PIN_Y10 3.3-V LVTTL
sdRamData[5] Input PIN_AA9 3.3-V LVTTL
sdRamData[6] Input PIN_AB8 3.3-V LVTTL
sdRamData[7] Input PIN_AA8 3.3-V LVTTL
sdRamData[8] Input PIN_U10 3.3-V LVTTL
sdRamData[9] Input PIN_T10 3.3-V LVTTL
sdRamData[10] Input PIN_U11 3.3-V LVTTL
sdRamData[11] Input PIN_R10 3.3-V LVTTL
sdRamData[12] Input PIN_R11 3.3-V LVTTL
sdRamData[13] Input PIN_U12 3.3-V LVTTL
sdRamData[14] Input PIN_R12 3.3-V LVTTL
sdRamData[15] Input PIN_P12 3.3-V LVTTL
sdSCLK Output PIN_L19 3.3-V LVTTL
serSelect Input PIN_L17 3.3-V LVTTL
sramAddress[0] Output PIN_G1 3.3-V LVTTL
sramAddress[1] Output PIN_L1 3.3-V LVTTL
sramAddress[2] Output PIN_N1 3.3-V LVTTL
sramAddress[3] Output PIN_U1 3.3-V LVTTL
sramAddress[4] Output PIN_Y3 3.3-V LVTTL
sramAddress[5] Output PIN_W2 3.3-V LVTTL
sramAddress[6] Output PIN_U2 3.3-V LVTTL
sramAddress[7] Output PIN_N2 3.3-V LVTTL
sramAddress[8] Output PIN_G2 3.3-V LVTTL
sramAddress[9] Output PIN_E7 3.3-V LVTTL
sramAddress[10] Output PIN_C6 3.3-V LVTTL
sramAddress[11] Output PIN_D9 3.3-V LVTTL
sramAddress[12] Output PIN_A5 3.3-V LVTTL
sramAddress[13] Output PIN_B7 3.3-V LVTTL
sramAddress[14] Output PIN_A8 3.3-V LVTTL
sramAddress[15] Output PIN_A10 3.3-V LVTTL
sramAddress[16] Output PIN_A7 3.3-V LVTTL
sramAddress[17] Output PIN_B6 3.3-V LVTTL
sramAddress[18] Output PIN_B5 3.3-V LVTTL
sramAddress[19] Output PIN_E9 3.3-V LVTTL
sramData[0] Bidir PIN_C1 3.3-V LVTTL
sramData[1] Bidir PIN_G6 3.3-V LVTTL
sramData[2] Bidir PIN_G8 3.3-V LVTTL
sramData[3] Bidir PIN_F7 3.3-V LVTTL
sramData[4] Bidir PIN_H8 3.3-V LVTTL
sramData[5] Bidir PIN_H6 3.3-V LVTTL
sramData[6] Bidir PIN_C2 3.3-V LVTTL
sramData[7] Bidir PIN_D3 3.3-V LVTTL
txd1 Output PIN_G10 3.3-V LVTTL
vSync Output PIN_A14 3.3-V LVTTL
videoB0 Output PIN_B13 3.3-V LVTTL
videoB1 Output PIN_A13 3.3-V LVTTL
videoG0 Output PIN_D13 3.3-V LVTTL
videoG1 Output PIN_C13 3.3-V LVTTL
videoR0 Output PIN_E12 3.3-V LVTTL
videoR1 Output PIN_D12 3.3-V LVTTL
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 07:21:26  July 04, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		TS2_68000_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEFA2F23I7
set_global_assignment -name TOP_LEVEL_ENTITY TS2_68000_Top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:21:26  JULY 04, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
# Clock and reset
set_location_assignment PIN_M9 -to i_CLOCK_50
set_location_assignment PIN_N16 -to i_n_reset
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_n_reset
# Serial
set_location_assignment PIN_B11 -to i_cts1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_cts1
set_location_assignment PIN_F10 -to o_rts1
set_location_assignment PIN_C11 -to i_rxd1
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_rxd1
set_location_assignment PIN_G10 -to o_txd1
set_location_assignment PIN_L17 -to i_serSelect
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_serSelect
# SRAM
set_location_assignment PIN_E2 -to o_n_sRamCS
set_location_assignment PIN_L2 -to o_n_sRamOE
set_location_assignment PIN_D6 -to o_n_sRamWE
set_location_assignment PIN_E9 -to o_sramAddress[19]
set_location_assignment PIN_B5 -to o_sramAddress[18]
set_location_assignment PIN_B6 -to o_sramAddress[17]
set_location_assignment PIN_A7 -to o_sramAddress[16]
set_location_assignment PIN_A10 -to o_sramAddress[15]
set_location_assignment PIN_A8 -to o_sramAddress[14]
set_location_assignment PIN_B7 -to o_sramAddress[13]
set_location_assignment PIN_A5 -to o_sramAddress[12]
set_location_assignment PIN_D9 -to o_sramAddress[11]
set_location_assignment PIN_C6 -to o_sramAddress[10]
set_location_assignment PIN_E7 -to o_sramAddress[9]
set_location_assignment PIN_G2 -to o_sramAddress[8]
set_location_assignment PIN_N2 -to o_sramAddress[7]
set_location_assignment PIN_U2 -to o_sramAddress[6]
set_location_assignment PIN_W2 -to o_sramAddress[5]
set_location_assignment PIN_Y3 -to o_sramAddress[4]
set_location_assignment PIN_U1 -to o_sramAddress[3]
set_location_assignment PIN_N1 -to o_sramAddress[2]
set_location_assignment PIN_L1 -to o_sramAddress[1]
set_location_assignment PIN_G1 -to o_sramAddress[0]
set_location_assignment PIN_C1 -to io_sramData[0]
set_location_assignment PIN_G6 -to io_sramData[1]
set_location_assignment PIN_G8 -to io_sramData[2]
set_location_assignment PIN_F7 -to io_sramData[3]
set_location_assignment PIN_H8 -to io_sramData[4]
set_location_assignment PIN_H6 -to io_sramData[5]
set_location_assignment PIN_C2 -to io_sramData[6]
set_location_assignment PIN_D3 -to io_sramData[7]
# External SD Card
set_location_assignment PIN_M22 -to o_sdCS
set_location_assignment PIN_L18 -to i_sdMISO
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to i_sdMISO
set_location_assignment PIN_L22 -to o_sdMOSI
set_location_assignment PIN_L19 -to o_sdSCLK
set_location_assignment PIN_D17 -to o_driveLED
# Video
set_location_assignment PIN_A15 -to o_hSync
set_location_assignment PIN_A14 -to o_vSync
set_location_assignment PIN_D12 -to o_videoR1
set_location_assignment PIN_E12 -to o_videoR0
set_location_assignment PIN_C13 -to o_videoG1
set_location_assignment PIN_D13 -to o_videoG0
set_location_assignment PIN_A13 -to o_videoB1
set_location_assignment PIN_B13 -to o_videoB0
# PS/2
set_location_assignment PIN_AA2 -to io_ps2Clk
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_ps2Clk
set_location_assignment PIN_AA1 -to io_ps2Data
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_ps2Data
# 50-pin I/O Connector
set_location_assignment PIN_AB15 -to IO_PIN[3]
set_location_assignment PIN_AA15 -to IO_PIN[4]
set_location_assignment PIN_Y14 -to IO_PIN[5]
set_location_assignment PIN_Y15 -to IO_PIN[6]
set_location_assignment PIN_AB17 -to IO_PIN[7]
set_location_assignment PIN_AB18 -to IO_PIN[8]
set_location_assignment PIN_Y16 -to IO_PIN[9]
set_location_assignment PIN_Y17 -to IO_PIN[10]
set_location_assignment PIN_AA17 -to IO_PIN[11]
set_location_assignment PIN_AA18 -to IO_PIN[12]
set_location_assignment PIN_AA19 -to IO_PIN[13]
set_location_assignment PIN_AA20 -to IO_PIN[14]
set_location_assignment PIN_Y19 -to IO_PIN[15]
set_location_assignment PIN_Y20 -to IO_PIN[16]
set_location_assignment PIN_AB20 -to IO_PIN[17]
set_location_assignment PIN_AB21 -to IO_PIN[18]
set_location_assignment PIN_AB22 -to IO_PIN[19]
set_location_assignment PIN_AA22 -to IO_PIN[20]
set_location_assignment PIN_Y22 -to IO_PIN[21]
set_location_assignment PIN_W22 -to IO_PIN[22]
set_location_assignment PIN_W21 -to IO_PIN[23]
set_location_assignment PIN_Y21 -to IO_PIN[24]
set_location_assignment PIN_V21 -to IO_PIN[25]
set_location_assignment PIN_U22 -to IO_PIN[26]
set_location_assignment PIN_W19 -to IO_PIN[27]
set_location_assignment PIN_V20 -to IO_PIN[28]
set_location_assignment PIN_U20 -to IO_PIN[29]
set_location_assignment PIN_U21 -to IO_PIN[30]
set_location_assignment PIN_T22 -to IO_PIN[31]
set_location_assignment PIN_R22 -to IO_PIN[32]
set_location_assignment PIN_R21 -to IO_PIN[33]
set_location_assignment PIN_P22 -to IO_PIN[34]
set_location_assignment PIN_T19 -to IO_PIN[35]
set_location_assignment PIN_T20 -to IO_PIN[36]
set_location_assignment PIN_P17 -to IO_PIN[37]
set_location_assignment PIN_P16 -to IO_PIN[38]
set_location_assignment PIN_N21 -to IO_PIN[39]
set_location_assignment PIN_N20 -to IO_PIN[40]
set_location_assignment PIN_M20 -to IO_PIN[41]
set_location_assignment PIN_M21 -to IO_PIN[42]
set_location_assignment PIN_N19 -to IO_PIN[43]
set_location_assignment PIN_M18 -to IO_PIN[44]
# SDRAM
set_location_assignment PIN_AA7 -to o_sdram_cas
set_location_assignment PIN_V9 -to o_sdram_cke
set_location_assignment PIN_AB11 -to o_sdram_clk
set_location_assignment PIN_AB5 -to o_sdram_cs
set_location_assignment PIN_AB7 -to o_sdram_ldqm
set_location_assignment PIN_V10 -to o_sdram_udqm
set_location_assignment PIN_AB6 -to o_sdram_ras
set_location_assignment PIN_W9 -to o_sdram_we
set_location_assignment PIN_P9 -to o_sdram_ba[1]
set_location_assignment PIN_T7 -to o_sdram_ba[0]
set_location_assignment PIN_Y9 -to o_sdram_addr[12]
set_location_assignment PIN_T9 -to o_sdram_addr[11]
set_location_assignment PIN_R6 -to o_sdram_addr[10]
set_location_assignment PIN_W8 -to o_sdram_addr[9]
set_location_assignment PIN_T8 -to o_sdram_addr[8]
set_location_assignment PIN_U8 -to o_sdram_addr[7]
set_location_assignment PIN_V6 -to o_sdram_addr[6]
set_location_assignment PIN_U7 -to o_sdram_addr[5]
set_location_assignment PIN_U6 -to o_sdram_addr[4]
set_location_assignment PIN_N6 -to o_sdram_addr[3]
set_location_assignment PIN_N8 -to o_sdram_addr[2]
set_location_assignment PIN_P7 -to o_sdram_addr[1]
set_location_assignment PIN_P8 -to o_sdram_addr[0]
set_location_assignment PIN_P12 -to io_sdram_data[15]
set_location_assignment PIN_R12 -to io_sdram_data[14]
set_location_assignment PIN_U12 -to io_sdram_data[13]
set_location_assignment PIN_R11 -to io_sdram_data[12]
set_location_assignment PIN_R10 -to io_sdram_data[11]
set_location_assignment PIN_U11 -to io_sdram_data[10]
set_location_assignment PIN_T10 -to io_sdram_data[9]
set_location_assignment PIN_U10 -to io_sdram_data[8]
set_location_assignment PIN_AA8 -to io_sdram_data[7]
set_location_assignment PIN_AB8 -to io_sdram_data[6]
set_location_assignment PIN_AA9 -to io_sdram_data[5]
set_location_assignment PIN_Y10 -to io_sdram_data[4]
set_location_assignment PIN_AB10 -to io_sdram_data[3]
set_location_assignment PIN_AA10 -to io_sdram_data[2]
set_location_assignment PIN_Y11 -to io_sdram_data[1]
set_location_assignment PIN_AA12 -to io_sdram_data[0]
# 
set_global_assignment -name VHDL_FILE TS2_68000_Top.vhd
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/UART/BaudRate6850.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/SDCARD/Older_SD_Controllers/sd_controller_NealC.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/COUNTER/n-bit-gray-counter.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/Debounce/LongDebounce/debounce.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/SBCTextDisplayRGB.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/SansBoldRomReduced.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/SansBoldRom.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/DisplayRam2K.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/DisplayRam1K.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/CGABoldRomReduced.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/TERMINAL/CGABoldRom.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/UART/bufferedUART.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/CPU/M68000/TG68K_2013/TG68KdotC_Kernel.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/CPU/M68000/TG68K_2013/TG68K_Pack.vhd"
set_global_assignment -name VHDL_FILE "../../MultiComp (VHDL Template)/Components/CPU/M68000/TG68K_2013/TG68K_ALU.vhd"
set_global_assignment -name VHDL_FILE Components/RAM_16Kx16.vhd
set_global_assignment -name VHDL_FILE Components/RAM_4Kx16.vhd
set_global_assignment -name QIP_FILE Components/Monitor_68K_ROM.qip
set_global_assignment -name QIP_FILE Components/RAM_8Kx16.qip
set_global_assignment -name QIP_FILE "../../MultiComp (VHDL Template)/Components/RAM_Internal/RAM_64KX16.qip"
set_global_assignment -name QIP_FILE RAM_32Kx16.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Power

  • 5V Power comes from the USB
  • 3.3V regulator on the RETRO-EP4CE15 Card installed
    • H2 pins 2-3 shorted on the RETRO-EP4CE15 card
    • Routes 3.3V from the 3.3V regulator to the J1 I/O connector
  • Power Distribution card
    • Gets 3.3V and GND from I1 on RETRO-EP4CE15 card
      • 2 sets of wires
    • Distributes 3.3V and GND to SD and DB-25 cards

Connectors

P2 - PS/2 Keyboard

  • Not every PS/2 keyboard works at 3.3V but many do

PS2 Mapping.PNG

  • PS2DAT = U7-8 = PIN_AA1
  • PS2CLK = U7-8 = PIN_AA2

VGA

J7 VGA.PNG

DB15HD VGA.PNG

Serial

  • USB B (full size)

RETROEP4-CE15 FTDI.PNG

RETROEP4-CE15 J7 SERIAL.PNG

SRAM

J7 SRAM.PNG

Cabling

Slide Switches/Reset Pushbutton

  • Slide switches are on the bottom of the box

MultiCompInBox P1992 cropped 720px.jpg

RETROEP4-CE15 J3.PNG

  • Pin assignments
    • PIN_L17 - Slide Switch 1 (top switch)
    • PIN_K17 - Slide Switch 2
    • PIN_K22 - Slide Switch 3
    • PIN_K21 - Slide Switch 4 (bottom switch)
  • Reset switch is on the front of the boz
    • PIN_N16 - Reset Switch

SD Card

J1 PIN SIGNAL COLOR SD PIN FPGA Pin DIR
2 3.3V ORG 7 VREG 3.3V OUT (PWR)
45 sdSCLK GRY 3 PIN_L19 OUT
46 sdMISO BLU 2 PIN_L18 IN
47 sdMOSI WHT 4 PIN_L22 OUT
48 sdCS VIO 5 PIN_M22 OUT
49 GND GRN 1 GND OUT (PWR)

DB-25 Female

DB25-02.PNG

DB25Female-02 SCHEMATIC.PNG

DB25F PINS.gif

DB-25 Cabling / Pin assignment

  • gpio2/gpio3 are from IOP-16 design
DB25 P1(DB25F) J1 Signal FPGA DB25 P1(DB25F) J1 Signal FPGA
1 25 26 NC
2 23 GND 14 24 GND
3 21 44 gpio3[7] PIN_M18 15 22 43 gpio3[6] PIN_N19
4 19 42 gpio3[5] PIN_M21 16 20 41 gpio3[4] PIN_M20
5 17 40 gpio3[3] PIN_N20 17 18 39 gpio3[2] PIN_N21
6 15 38 gpio3[1] PIN_P16 18 16 37 gpio3[0] PIN_P17
7 13 36 gpio2[7] PIN_T20 19 14 35 gpio2[6] PIN_T19
8 11 34 gpio2[5] PIN_P22 20 12 33 gpio2[4] PIN_R21
9 9 32 gpio2[3] PIN_R22 21 10 31 gpio2[2] PIN_T22
10 7 30 gpio2[1] PIN_U21 22 8 29 gpio2[0] PIN_U20
11 5 23 6
12 3 24 4
13 1 +3.3V 25 2 +3.3V

Programming the FPGA EEPROM

  • File
  • Convert Programming File
  • Configuration Device = EPCQ64
  • Mode = Active Serial
  • Programming File Type: *.jic
  • Advanced = Check both Disables...
  • Select Flash Loader
  • Add Device = Cyclone V and 5CEFA2
  • Select SOF Data
  • Select Add File and select the .sof file
  • Generate
  • In Tools, Programmer
  • Mode: JTAG
  • Add file and select the .jic file
  • Select Program/Configure
  • Takes a while to program
  • Press button near VGA

Front Panel I/O Demo Video

IOP-16 LEDs P18125 720px.jpg

USB Panel Mount Connector

  • USB Blaster embedded in the enclosure
  • USB Mini connector

USB BLASTER JACK.PNG

USB Extender Cable.jpg

Build Photos

  • White-On-Clear P-Touch labels were used to mark front/rear panels
  • Rear viewL USB Blaster, VGA, USB-B, PS/2 Keyboard

MultiCompInBox P1983 cropped 720px.jpg

  • Top view: FPGA, SD Card, PD01 Power Distribution Card, USB Blaster, internal cabling

MultiCompInBox P1985 cropped 720px.jpg

  • USB Blaster attached to inside of rear panel using with Double Stick Tape

MultiCompInBox P1986 720px.jpg

  • Right inside of box: SD Card, Reset switch, PD01 Power Distribution card

MultiCompInBox P1987 cropped 720pxV.jpg

  • DB-25 connector card (not shown in enclosure)

MultiCompInBox P1991 cropped.jpg

  • Selection Switch on the bottom of the box
  • 4 switches

MultiCompInBox P1992 cropped 720px.jpg

Enclosure

YaeCCC CASE.PNG

GitHub Repository