WaveShare CoreEP4CE6 EP4CE6E22C8N FPGA Board

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EP4CE6E22C8N FPGA Board

RETRO-EP4 Board

Features

CoreEP4CE6-intro.jpg

  1. EP4CE6E22C8N:the ALTERA Cyclone IV FPGA device which features:
  2. AMS1117-3.3, 3.3V voltage regulator
  3. AMS1117-2.5, 2.5V voltage regulator
  4. AMS1117-1.2, 1.2V voltage regulator
  5. EPCS16, onboard serial FLASH memory, for storing code
  6. Power indicator
  7. LEDs
  8. Reset button
  9. nCONFIG button: for re-configuring the FPGA chip, the equivalent of power reseting
  10. Power switch
  11. 50MHz active crystal oscillator
  12. 5V DC jack
  13. JTAG interface: for debugging/programming
  14. FPGA pins expander, VCC, GND and all the I/O ports are accessible on 2x20 expansion connectors for further expansion
  15. LED jumpers

Details of the FPGA

  • EP4CE6E22C8N: the ALTERA Cyclone IV FPGA device which features:
    • Operating Frequency: 50MHz
    • Operating Voltage: 1.15V~3.465V
    • Package: QFP144
    • I/Os: 80
    • LEs: 6272
    • RAM: 270kb
      • 30 of 9K memory blocks
    • PLLs: 2
    • 18-bit x 18-bit multipliers: 15
    • Debugging/Programming: supports JTAG

EP4CE6 Data Sheet Part Selector.jpg

Block Diagram

(From WaveShare site) FPGA_Cyclone_Device_Design.jpg

EP4CE6E22C8N Device Resources

EP4CE6 Device List.jpg

EP4CE6E22C8N FPGA Board Features

EP4CE6 Breakout Board

  • We made an ODAS form factor breakout card for the EP4 card

FPGA Board - Connectors

FPGA Board - JTAG

  • Connector is used for programming the card

JTAG-CPLD.jpg

FPGA Board Pinout

CoreEP4CE6-IOConns.jpg

Indicators

Power LED

  • The board has a power LED which illuminates when power is applied and switched on.

User Controlled LEDs

  • LED1 - JP0 removes - connects to IO3
  • LED2 - JP2 removes - connects to IO7
  • LED3 - JP3 removes - connects to IO10
  • LED4 - JP4 removes - connects to IO11

Switches

  • Power Switch
    • Only disconnects power supplied from the on-board barrel power connector
    • Power in from the I/O connector is not switched
  • Reset Switch connects to pin 125 on the FPGA
  • nCONFIG Switch connects to pin 14 on the FPGA

I/O Pin Mapping

FPGA Pin Function Notes
1-2 IO
3 LED1 LED
4 GND Power
5 VCC1.2 Power
6 ASD0 EPCS
7 LED2 LED
8 NCS0 EPCS
9 VCC3.3 Resistor 10K pullup to VCC
10 LED3 LED
11 LED4 LED
12 DCLK EPCS
13 DATA0 EPCS
14 nCONFIG Config button
15 TDI JTAG
16 TCK JTAG
17 VCC3.3 Power
18 TMS JTAG
19 GND Power
20 TDO JTAG
21-22 nCE Hard tied to ground
23 CLK 50 MHz oscillator
27 GND Power
28 IO
29 VCC1.2 Core power
30-34 IO
35 VCC2.5 Power
36 GND Power
37 VCC1.2 Core power
38-39 IO
40 VCC3.3 Power
41 GND Power
42-44 IO
45 VCC1.2 Power
46 IO
47 VCC3.3 IO Voltage
48 GND Power
49-55 IO
56 VCC3.3 Power
57 GND Power
48-60 IO
61 VCC1.2 Power
62 VCC3.3 Power
63 GND Power
64-77 IO
78 VCC1.2 Core power
79 GND Power
80 IO
81 VCC3.3 Power
82 GND Power
83-87 IO
92 VCC3.3 Pullup through 10K
94 VCC3.3 Pullup through 10K
95-96 GND Power
97 VCC3.3 Pullup through 10K
98-101 IO
102 VCC1.2 Power
103-106 IO
107 VCC2.5 Power
108 GND Power
109 VCC1.2 Core power
110-115 IO
116 VCC1.2 Power
117 VCC3.3 Pullup through 10K
118 GND Power
119-121 IO
122 VCC3.3 Pullup through 10K
123 GND Power
124 IO
125 RESET
126-129 IO
130 VCC3.3 Pullup through 10K
131 GND Power
132-133 IO
134 VCC1.2 Power
135-138 IO
139 VCC3.3 Pullup through 10K
140 GND Power
141-144 IO

Pin List

set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY Blink1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:13:02  MARCH 09, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3 V"
set_location_assignment	PIN_23	-to	CLK
set_location_assignment	PIN_125	-to	RESET
set_location_assignment	PIN_3	-to	LED[0]
set_location_assignment	PIN_7	-to	LED[1]
set_location_assignment	PIN_10	-to	LED[2]
set_location_assignment	PIN_11	-to	LED[3]
set_location_assignment	 PIN_12	-to	EPCS_CLK
set_location_assignment	 PIN_13	-to	EPCS_DATA0
set_location_assignment	 PIN_8	-to	EPCS_SCE
set_location_assignment	  PIN_6	-to	EPCS_SDO
set_location_assignment	H_LEFT_1  -to	GND
set_location_assignment	H_LEFT_2  -to	3.3V
set_location_assignment	H_LEFT_3  -to	PIN_59
set_location_assignment	H_LEFT_4  -to	PIN_60
set_location_assignment	H_LEFT_5  -to	PIN_64
set_location_assignment	H_LEFT_6  -to	PIN_65
set_location_assignment	H_LEFT_7  -to	PIN_66
set_location_assignment	H_LEFT_8  -to	PIN_67
set_location_assignment	H_LEFT_9  -to	PIN_68
set_location_assignment	H_LEFT_10 -to	PIN_69
set_location_assignment	H_LEFT_11 -to	PIN_70
set_location_assignment	H_LEFT_12 -to	PIN_71
set_location_assignment	H_LEFT_13 -to	PIN_72
set_location_assignment	H_LEFT_14 -to	PIN_73
set_location_assignment	H_LEFT_15 -to	PIN_74
set_location_assignment	H_LEFT_16 -to	PIN_75
set_location_assignment	H_LEFT_17 -to	PIN_76
set_location_assignment	H_LEFT_18 -to	PIN_77
set_location_assignment	H_LEFT_19 -to	PIN_80
set_location_assignment	H_LEFT_20 -to	PIN_83
set_location_assignment	H_LEFT_21 -to	PIN_84
set_location_assignment	H_LEFT_22 -to	PIN_85
set_location_assignment	H_LEFT_23 -to	GND
set_location_assignment	H_LEFT_24 -to	5V
set_location_assignment	H_LEFT_25 -to	PIN_86
set_location_assignment	H_LEFT_26 -to	PIN_87
set_location_assignment	H_LEFT_27 -to	PIN_98
set_location_assignment	H_LEFT_28 -to	PIN_99
set_location_assignment	H_LEFT_29 -to	PIN_100	
set_location_assignment	H_LEFT_30 -to	PIN_101
set_location_assignment	H_LEFT_31 -to	PIN_103
set_location_assignment	H_LEFT_32 -to	PIN_104
set_location_assignment	H_LEFT_33 -to	PIN_105
set_location_assignment	H_LEFT_34 -to	PIN_106
set_location_assignment	H_LEFT_35 -to	PIN_110
set_location_assignment	H_LEFT_36 -to	PIN_111
set_location_assignment	H_LEFT_37 -to	PIN_112
set_location_assignment	H_LEFT_38 -to	PIN_113
set_location_assignment	H_LEFT_39 -to	PIN_114
set_location_assignment	H_LEFT_40 -to	PIN_115
set_location_assignment	H_LEFT_41 -to	PIN_119
set_location_assignment	H_LEFT_42 -to	PIN_120
set_location_assignment	H_LEFT_43 -to	PIN_121
set_location_assignment	H_LEFT_44 -to	PIN_124

# Herder_Right(just for reference, can't be Actual Settings of Tcl)
set_location_assignment	H_Right_1 -to		GND
set_location_assignment	H_Right_2 -to		3.3V
set_location_assignment	H_Right_3 -to		PIN_58
set_location_assignment	H_Right_4 -to		PIN_55
set_location_assignment	H_Right_5 -to		PIN_54
set_location_assignment	H_Right_6 -to		PIN_53
set_location_assignment	H_Right_7 -to		PIN_52
set_location_assignment	H_Right_8 -to		PIN_51
set_location_assignment	H_Right_9 -to		PIN_50
set_location_assignment	H_Right_10 -to	PIN_49
set_location_assignment	H_Right_11 -to	PIN_46
set_location_assignment	H_Right_12 -to	PIN_44
set_location_assignment	H_Right_13 -to	PIN_43
set_location_assignment	H_Right_14 -to	PIN_42
set_location_assignment	H_Right_15 -to	PIN_39
set_location_assignment	H_Right_16 -to	PIN_38
set_location_assignment	H_Right_17 -to	PIN_34
set_location_assignment	H_Right_18 -to	PIN_33
set_location_assignment	H_Right_19 -to	PIN_32
set_location_assignment	H_Right_20 -to	PIN_31
set_location_assignment	H_Right_21 -to	PIN_30
set_location_assignment	H_Right_22 -to	PIN_28
set_location_assignment	H_Right_23 -to	GND
set_location_assignment	H_Right_24 -to	5V
set_location_assignment	H_Right_25 -to	PIN_11
set_location_assignment	H_Right_26 -to	PIN_10
set_location_assignment	H_Right_27 -to	PIN_7
set_location_assignment	H_Right_28 -to	PIN_3
set_location_assignment	H_Right_29 -to	PIN_2
set_location_assignment	H_Right_30 -to	PIN_1
set_location_assignment	H_Right_31 -to	PIN_144
set_location_assignment	H_Right_32 -to	PIN_143
set_location_assignment	H_Right_33 -to	PIN_142
set_location_assignment	H_Right_34 -to	PIN_141
set_location_assignment	H_Right_35 -to	PIN_138
set_location_assignment	H_Right_36 -to	PIN_137
set_location_assignment	H_Right_37 -to	PIN_136
set_location_assignment	H_Right_38 -to	PIN_135
set_location_assignment	H_Right_39 -to	PIN_133
set_location_assignment	H_Right_40 -to	PIN_132
set_location_assignment	H_Right_41 -to	PIN_129
set_location_assignment	H_Right_42 -to	PIN_128
set_location_assignment	H_Right_43 -to	PIN_127
set_location_assignment	H_Right_44 -to	PIN_126


set_location_assignment PIN_58 -to PB

FPGA Board Physical

CoreEP4CE6-size-2.jpg

Programming the EPCS16 Flash

  • The Cyclone II card has separate connectors for JTAG and AS which lets the compiled FPGA code be stored temporarily (into the FPGA) or permanently (into the Flash EEPROM for loading into the FPGA at startup)
  • This card does not have two separate connectors
    • Card uses the single JTAG connector for code download
  • The card can be temporarily or permanently changed - but it's done with some special methods
    • Temporary programming does not persist after power cycling (or reset)
    • Permanent programming requires downloading the FPGA into the attached Serial EEPROM
  • WaveShare site has sketchy details on how to program the EEPROM
    • This is attempt to document the steps I took to make it work

EP4-Programming.PNG

Create sof file

  • In Quartus create code
  • Device: EP4CE6E22C8
  • Compile the part
    • Processing > Start Compile
  • This results in a .sof file
    • .sof file is an sram download which puts the logic into the FPGA but does not store it permanently in the EEPROM

Create jic file

  • Ap Note on this process
  • Convert .sof file to .jic file
    • jic file is a JTAG Indirect Configuration file
      • jic file is downloaded through the FPGA into the EEPROM
      • File is brought through the FPGA which will be in a soft programming mode
    • File > Convert Programming File
    • If Conversion setup was previously saved then
      • Open Conversion Setup Data...
      • Select the file
      • If via this method then the next couple of steps can be skipped
    • If this is the first time then the next few steps need to be followed
    • Programming file type: JTAG Indirect Configuration file (.jic)
    • Configuration device: EPCS16
    • Set output file name
      • Make sure path is correct since the previous path seems to persist
  • Two "segments" in the Input Files to convert section
    • Flash Loader: EP4CE6
    • SOF Data: xxx.sof
  • Verify screen looks similar to this

Conv Prog File.PNG

  • Click Generate
    • Overwrite file (if needed)
  • Save Conversion Setup so you don't need to do this next time
  • Close

Program EEPROM

  • Back in Quartus Programmer
    • In Quartus select Program Device (Open Programmer)
  • Tools | Options
    • Select Use the enhanced mode Serial Flash Loader (SFL) IP for factory default helper image
  • Autodetect device
    • EP4CE6E22 shows up in preview window below
  • Select device by clicking on it
  • Right click on device
  • Edit
    • Attach flash device
    • Select Flash Device: EPCS16
  • Click on EPCS16 and change file
  • Select Program/Configure box and the Factory default enhanced... line will appear
  • Select Start
  • Program Device with the setup below
  • If you did this before the screen is probably already correctly filled out
  • Note this has the FPGA on the card and the serial EEPROM shown as a connection from the FPGA
    • The FPGA has "Factory default enhanced SFL image" and is assigned to the EP4CE6
    • The .jic file which was created in the previous steps is assigned to the EPCS16
  • Mode should be JTAG since the connection to the card is via the one JTAG connector
  • Select Program/configure
    • The SFL image is a soft loader which lets the FPGA control the EEPROM

JIC File-5-Program.PNG

  • Start
  • The FPGA is left with only the Serial programmer
  • Remove power and repower up the card to have change take effect

VHDL Examples

Comparison of EP2 and EP4 Boards

Feature EP2C5 EP4CE6 Delta (%)
RAM (bits) 119808 270000 125.36%
RAM (bytes) 14976 33750
Logic Elements 4608 6272 36.11%
LAB 288 392 36.11%
I/Os 89 91
Freq (Mhz) 260 200
Cost (chip/Mouser) $14.72 $11.95 -18.82%