ZrTech V2 EP4CE6 Cyclone IV FPGA EP4CE6E22C8N Development Board USB V2

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EP4-FPGA-VGA.jpg

Features of the EasyFPGA-Cyclone-IV development board

  • Manufacturer: ZRTech V2.00 (Ebay search)
  • FPGA : Altera Cyclone IV FPGA EP4CE6E22C8N
  • JTAG Port : On-board JTAG Port for programming
  • Flash:32Mbit NOR Flash (W25Q32) memory ,Support Byte (8-bits)/Word (16-bits) mode
    • Series Flash: EPCS4SI8N 4Mbit
  • SDRAM
  • PS/2 Port
    • Provides the PS2 port for Mouse and Keyboard
  • Pushbutton switches
    • 4 User Keys - Normally high; generates one active-low pulse when the switch is pressed
  • Infrared Receiver
    • Communicate with a Remoter for wireless control
  • General User Interfaces
    • 4 User LEDs (Active low)
    • 4 digit 7-segment displays (Active high)
    • Active Type Buzzer
  • System Clock inputs :48MHz oscillator (this might actually be 50 MHz???)
  • VGA output : Uses a 8-bit resistor-network DAC under RGB565 Mode. With 15-pin high-density D-sub connector
  • TLC549C A/D converter
    • 8-Bit, 40 kSPS ADC Serial Out, Low Power
    • I/O CLOCK input frequency of the TLC549 is specified up to 1.1 MHz
    • Uses a SMA port for AD signal input
    • Jumper:Selection for External or on-board A/D signal source.
  • On-board USB interface with status and Power LED.
    • PL2303 USB to TTL/RS232 Module
    • USB-Mini connector
  • 26-PIN Expansion Headers
    • Altera Cyclone IV I/O pins, as well as 3 power and ground lines, are brought out to the 26-pin expansion connectors
    • Unfortunately, these are mostly shared with other functions on the card
  • Voltage Regulator Circuit :Provides 1.2V,2.5V and 3.3V for system power supply

EP4CE6E22C8N Device Resources

EP4CE6 Device List.jpg

Schematic of the card

I/O Connector

  • The I/O connector shares pins with the VGA and PS/2 connections.
    • This is a problem if VGA and PS/2 are used since there's no I/O connections left

IO Connector 26 pin.jpg

Programming the Flash

The card can be temporarily or permanently changed - but it's done with some special methods

  • Temporary programming does not persist after power cycling (or reset)
  • Permanent programming requires downloading the FPGA into the attached Serial EEPROM

This is the procedure for programming the flash on the card.

Create sof file

  • In Quartus create code
    • Device: EP4CE6E22C8
  • Compile the part
    • Processing > Start Compile
  • This results in a .sof file
    • .sof file is an sram download which puts the logic into the FPGA but does not store it permanently in the EEPROM

Convert sof file into jic file

  • AN370 - Ap Note on this process
  • jic file is a JTAG Indirect Configuration file
    • jic file is downloaded through the FPGA into the EEPROM
    • File is brought through the FPGA which will be in a soft programming mode
  • File > Convert Programming File
  • If Conversion setup was previously saved then
    • Open Conversion Setup Data...
    • Select the file
    • If via this method then the next couple of steps can be skipped
    • If this is the first time then the next few steps need to be followed
  • Programming file type: .jic
  • Configuration device: EPCS4
  • Set output file name
    • Make sure path is correct since the previous path seems to persist
  • Two "segments" in the Input Files to convert section
    • Flash Loader: EP4CE6
    • SOF Data: xxx.sof
  • Verify screen looks similar to this

Programming EPROM.PNG

Programmer

  • Back in Quartus Programmer
    • In Quartus select Program Device (Open Programmer)
  • Tools | Options
    • Select Use the enhanced mode Serial Flash Loader (SFL) IP for factory default helper image
  • Autodetect device
    • EP4CE6E22 shows up in preview window below
  • Select device by clicking on it
  • Right click on device
  • Edit
    • Attach flash device
    • Select Flash Device: EPCS4
  • Click on EPCS4 and change file
  • Select Program/Configure box and the Factory default enhanced... line will appear
  • Select Start
  • Program Device with the setup below
  • If you did this before the screen is probably already correctly filled out
  • Note this has the FPGA on the card and the serial EEPROM shown as a connection from the FPGA
    • The FPGA has "Factory default enhanced SFL image" and is assigned to the EP4CE6
    • The .jic file which was created in the previous steps is assigned to the EPCS16
  • Mode should be JTAG since the connection to the card is via the one JTAG connector
  • Select Program/configure
    • The SFL image is a soft loader which lets the FPGA control the EEPROM

Programming EPROM-2.PNG

PL-2303 USB-Serial Drivers and Windows 8/10

  • The zrTech card uses the Prolific PL-2303HX part which does not have Windows 8 and Windows 10 support\
  • Fix described here
  • Prolific has a problem with PL-2303HX counterfeit chips
    • From the Prolific website
Warning Letter on Counterfeit Products   Hot News
Warning Notice:
It is confirmed that counterfeit (fake) PL-2303HX Rev A USB to Serial Controller ICs 
using Prolific's trademark logo and device drivers were being sold in the China market. 
Counterfeit IC products show exactly the same outside chip markings but generally 
are of poor quality and causes driver compatibility issues. We issue this warning 
to all our customers and consumers to avoid confusion and false purchase. 
Only buy from Prolific authorized distributors.
Please be warned also that selling counterfeit products are illegal and punishable by 
civil and criminal courts according to the trademark, copyright, and intellectual 
properties laws and regulations. Prolific will take proper and severe actions to cease 
and confiscate these counterfeit products. Prolific also prohibits the distribution 
of any PL-2303 drivers (including download links) without written permission from Prolific.

Prolific advices end-users to only purchase branded cable products with company name contact 
information for service and support in case you suspect a counterfeit chip inside. 
You may also contact Prolific to provide the vendor information.

PL-2303HX Rev A (or PL-2303HXA) also has been discontinued (EOL) since October 2012 
and does not support Windows 8 onwards. 
Prolific advises users to purchase cables/adapters with PL2303HXD (HX Rev D) chip.
  • In response, Prolific has taken a page out of the FTDI failure plan by disabling support
    • FTDI bricked a lot of parts until they were forced by market pressures to step back and re-enable support
  • If you do windows update your driver will be over-written and the chip will not work
  • This problem is widely reported on the Internet
  • Very few of the solutions work all that well
  • The only possibly viable solution is to "use a driver release older than 3.4"
    • Of course, Prolific doesn't put the older drivers on their website
  • The problem is that this solution is temporary
  • Solution from here
To avoid that, a recent workaround exist and has been published by Microsoft. 
It's a tool named wushowhide.diagcab ("Show and Hide Update"). 
It allow to inhibit the auto-update for a particular program or driver (Prolific in our case).
For more informations and where to download this tool, take a look at this article : 
KB3073930

GitHub Repository

On-Board Resources

LEDs

  • D2 - DS_DP = Pin 3
  • D3 - DS_G = Pin 2
  • D4 - DS_C = Pin 1
  • D5 - DS_D = Pin 141

Switches

  • S1 - uKEY3 - Key3 = Pin 88
  • S2 - uKEY2 - Key2 = Pin 91
  • S3 - uKEY1 - Key1 = Pin 90
  • S4 - RSTn - Key4 = Pin 89

Pin List

set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:07:01  MAY 10, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_13 -to ~ALTERA_DATA0~
set_location_assignment PIN_12 -to ~ALTERA_DCLK~
set_location_assignment PIN_8 -to ~ALTERA_FLASH_nCE_nCSO~
set_location_assignment PIN_6 -to ~ALTERA_ASDO_DATA1~set_global_assignment -name ENABLE_OCT_DONE OFF
--
set_location_assignment PIN_24 -to clk
set_location_assignment PIN_89 -to n_reset
--
set_location_assignment PIN_100 -to hsync
set_location_assignment PIN_101 -to vsync
set_location_assignment PIN_120 -to videoR0
set_location_assignment PIN_121 -to videoR1
set_location_assignment PIN_124 -to videoR2
set_location_assignment PIN_125 -to videoR3
set_location_assignment PIN_126 -to videoR4
set_location_assignment PIN_111 -to videoG0
set_location_assignment PIN_112 -to videoG1
set_location_assignment PIN_113 -to videoG2
set_location_assignment PIN_114 -to videoG3
set_location_assignment PIN_115 -to videoG4
set_location_assignment PIN_119 -to videoG5
set_location_assignment PIN_103 -to videoB0
set_location_assignment PIN_104 -to videoB1
set_location_assignment PIN_105 -to videoB2
set_location_assignment PIN_106 -to videoB3
set_location_assignment PIN_110 -to videoB4
--
set_location_assignment PIN_1 -to LED1
set_location_assignment PIN_2 -to LED2
set_location_assignment PIN_3 -to LED3
set_location_assignment PIN_141 -to LED4
--
set_location_assignment PIN_88 -to switch1
set_location_assignment PIN_91 -to switch2
set_location_assignment PIN_90 -to switch3
--
set_location_assignment PIN_99 -to ps2Clk
set_location_assignment PIN_98 -to ps2Data
--
set_location_assignment PIN_46 -to sras
set_location_assignment PIN_43 -to swe
set_location_assignment PIN_44 -to scas
set_location_assignment PIN_64 -to scke
set_location_assignment PIN_60 -to sclk
set_location_assignment PIN_74 -to scs
set_location_assignment PIN_77 -to saddr[0]
set_location_assignment PIN_80 -to saddr[1]
set_location_assignment PIN_83 -to saddr[2]
set_location_assignment PIN_84 -to saddr[3]
set_location_assignment PIN_72 -to saddr[4]
set_location_assignment PIN_71 -to saddr[5]
set_location_assignment PIN_70 -to saddr[6]
set_location_assignment PIN_69 -to saddr[7]
set_location_assignment PIN_68 -to saddr[8]
set_location_assignment PIN_67 -to saddr[9]
set_location_assignment PIN_76 -to saddr[10]
set_location_assignment PIN_66 -to saddr[11]
set_location_assignment PIN_65 -to saddr[12]
set_location_assignment PIN_73 -to sba[0]
set_location_assignment PIN_75 -to sba[1]
set_location_assignment PIN_30 -to sdata[0]
set_location_assignment PIN_28 -to sdata[1]
set_location_assignment PIN_32 -to sdata[2]
set_location_assignment PIN_31 -to sdata[3]
set_location_assignment PIN_33 -to sdata[4]
set_location_assignment PIN_34 -to sdata[5]
set_location_assignment PIN_38 -to sdata[6]
set_location_assignment PIN_39 -to sdata[7]
set_location_assignment PIN_58 -to sdata[8]
set_location_assignment PIN_55 -to sdata[9]
set_location_assignment PIN_54 -to sdata[10]
set_location_assignment PIN_53 -to sdata[11]
set_location_assignment PIN_52 -to sdata[12]
set_location_assignment PIN_51 -to sdata[13]
set_location_assignment PIN_50 -to sdata[14]
set_location_assignment PIN_49 -to sdata[15]
set_location_assignment PIN_42 -to sdqm[0]
set_location_assignment PIN_59 -to sdqm[1]
--
set_location_assignment PIN_143 -to seg7c[0]
set_location_assignment PIN_144 -to seg7c[1]
set_location_assignment PIN_1 -to seg7c[2]
set_location_assignment PIN_141 -to seg7c[3]
set_location_assignment PIN_142 -to seg7c[4]
set_location_assignment PIN_138 -to seg7c[5]
set_location_assignment PIN_2 -to seg7c[6]
set_location_assignment PIN_133 -to seg7en[0]
set_location_assignment PIN_136 -to seg7en[1]
set_location_assignment PIN_135 -to seg7en[2]
set_location_assignment PIN_137 -to seg7en[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sras
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to swe
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to saddr[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sba[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sba[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scas
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scke
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sclk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to scs
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdata[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdqm[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdqm[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7c[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7c[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7c[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7c[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7c[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7c[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7c[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7en[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7en[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7en[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to seg7en[3]
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to hsync
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nrsti
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rgb[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to vsync
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to pxr
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to bsyp
set_global_assignment -name VHDL_FILE vga.vhd
set_global_assignment -name VHDL_FILE top.vhd
set_global_assignment -name VHDL_FILE seg7.vhd
set_global_assignment -name VHDL_FILE sdramctrl.vhd
set_global_assignment -name VHDL_FILE rsthandler.vhd
set_global_assignment -name VHDL_FILE pll.vhd
set_global_assignment -name QIP_FILE pll.qip
set_global_assignment -name SOURCE_FILE pll.cmp
set_global_assignment -name VHDL_FILE memhandler.vhd
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name QIP_FILE vpll.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 

VGA Timing

  • Master Board Clock = 48 MHz = 20.8 nS
  • 640x480
  • 307,200 bits
  • Close to 25 MHz
    • Conflicts with the 48 MHz main oscillator speed

Multicomp Builds

M6809 VGA PS2 IntRAM(16K)

  • GitHub repository
    • 6809 CPU
    • 16K internal SRAM
    • Video
      • VGA
      • 80x25
    • PS/2 keyboard
    • 8K BASIC in ROM

UK101 16K Composite Video

  • GitHub repository
    • 6502 CPU
    • 16K internal SRAM
    • Video
      • Monochrome Composite Video
      • 48x16 characters
    • PS/2 keyboard
    • CEGMON machine code monitor
    • 8K BASIC in ROM

UK101 16K 64x32 VGA Video

EP4 Video Series

Our series of videos where we take a look at the board and get Multicomp running (the playlist).

Links