R32V2020 Condition Code Register
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Contents
r3 - Condition Code Register (CCR)
- r3 is the Condition Code Register (CCR)
- The CCR can only be affected by the result of ALU operations
- The CCR represents bits that represents the result of an ALU operation
d0 - Equal to Zero Flag
- =1 if the result of last ALU operation was equal to 0x0
- Used by BEZ conditional branch opcode
- Affected by ADS, MUL, QRS, ORS, XRS, LS1, RS1, RS1, LR1, RR1, RA1, ENS opcodes
d1 - Equal to One Flag
- =1 if the result of last ALU operation was equal to 0x1
- Used by BE1 conditional branch opcode
- Affected by ADS, MUL, QRS, ORS, XRS, LS1, RS1, RS1, LR1, RR1, RA1, ENS opcodes
d2 - Not Equal to Zero Flag
- =1 if the result of last ALU operation was not equal to 0x0
- Used by BNZ opcode
- Affected by ADS, MUL, QRS, ORS, XRS, LS1, RS1, RS1, LR1, RR1, RA1, ENS opcodes
d3 - Carry Clear Flag
- =1 if the result of last ALU operation produced a carry
- Used by BCC opcode
- Affected by ADS operation
d4 - Carry Set
- =1 if the result of last ALU operation did not produce a carry
- Used by BCS opcode
- Affected by ADS operation
d5 - Less than
- =1 if rSrc1 < rSrc2
- Used by the BLT opcode
- Affected by the CMP opcode
- Shows order of comparison
- branches to skip9
skip8: cmp r1,r0 ; test blt/bgt bgt failed ; should not take bgt blt skip9 ; should take blt bra failed skip9:
d6 - Greater than
- =1 if rSrc1 > rSrc2
- Used by the BGT opcode
- Affected by the CMP opcode
- branches to skip8
skip7: cmp r0,r1 ; test blt/bgt blt failed ; should not take blt bgt skip8 ; should take bgt bra failed skip8:
d7 - Equal
- =1 if rSrc1 = rSrc2
- Used by the BEQ opcode
- Affected by the CMP opcode
d8 - Not Equal
- =1 if rSrc1 <> rSrc2
- Used by the BNE opcode
- Affected by the CMP opcode