R32V2020 Debug and Troubleshooting

SignalTap Logic Analyzer

SignalTap is a logic analyzer built into Altera tools. From SignalTap II Logic Analyzer Tutorial

The SignalTap II Logic Analyzer allows you to probe signals inside of the fpga so you can view the waveforms. This allows you to debug your hardware. This is especially useful when you run into the situation where your mapped design works in simulation but not on the fpga.

To see the R32V2020 signals:

1. Hold nRST low on the board (S4 on the zrTech board).
2. Load the program into your RAM via the In-System Memory Editor
3. Click the “Run Analysis” button in the signal tap logic analyzer window (purple play button)
4. Release the nRST (S4 on the zrTech board). Your Design will operate on the memory and when the signal tap logic notices that your signals are no longer changing, it will stop the acquisition. You can view your signals by selecting the “Data” tab in the SignalTap II Logic Analyzer window.

Edit Instruction ROM contents (In-System Memory Editor)

• Connect to card JTAG connector via BitBlaster cable
• Select Hardware
• Scan Chain - loads current Instruction ROM from the target
• Click in the data area
• Manually type in the assembly opcode values
• On menu bar select Edit > Export to save as .HEX file

In System Memory Content Editor user manual

Why do I see the design entity sld_hub sld_hub_inst in my design?

• The sld_hub entity is an interface controller between the JTAG pins on your device and the following Quartus® II features that use the JTAG pins : SignalTap II Logic Analyzer/In-System Memory Content Editor

4 Hex Digit / Seven Segment Display

• The zrTech card has a four digit seven segment display that can display hex values
• Setting the upper two digits to the top 8 bits of the opcode and the lower two digits to the instruction address lower 8 bits
• Can verify visually if program halts or jumps back to self
• This interface could be moved to any location to monitor 16-bits