R32V2020 Performance
Revision as of 13:01, 10 April 2022 by Blwikiadmin (talk | contribs) (Created page with "= Design Status = * Un-optimized instruction queue ** Not yet a pipelined design * Using the card's 50 MHz oscillator ** 20 nS clock rate = Theoretical Performance = * 6 Cl...")
Contents
Design Status
- Un-optimized instruction queue
- Not yet a pipelined design
- Using the card's 50 MHz oscillator
- 20 nS clock rate
Theoretical Performance
- 6 Clocks per Instruction
- 20 nS/clock (50 MHz)
- 120 nS / instruction
- 8.33 MIPs
Measured Performance
First Performance Test
- 60 clocks, 10 instructions, 1.2 uS
<img src="https://user-images.githubusercontent.com/1524110/58422589-f230a200-8060-11e9-9e54-7effd69b2185.PNG"></img>
