Difference between revisions of "LB-65CXX-01"
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Line 24: | Line 24: | ||
* Pin differences | * Pin differences | ||
** Pin 1 | ** Pin 1 | ||
− | *** R65C02 = VSS | + | *** R65C02 = VSS J2:1-2 |
− | *** W65C02 = VPB | + | *** W65C02 = VPB J2:2-3 |
** Pin 5 | ** Pin 5 | ||
*** R65C02 = NC | *** R65C02 = NC |
Revision as of 19:58, 18 August 2024
Contents
Features
- 65C02 or 65C816 CPU
- 2 MHz Oscillator on card
- Reset switch/power monitor
- Address decoder PLD drives RAM/ROM/IO chip selects
- 100x50mm card
Design
CPU
- 65C02 or 65C816 CPU
- 2 MHz
R65C02 vs W65C92 CPUs
- Pin differences
- Pin 1
- R65C02 = VSS J2:1-2
- W65C02 = VPB J2:2-3
- Pin 5
- R65C02 = NC
- W65C02 = MLB
- Pin 36
- R65C02 = NC
- W65C02 = BE
- Pin 1
Oscillator
PLD
Name LB-65CXX-01_PLD; Partno ATF16V8B; Date 09/09/20; Revision 01; Designer DOUG G; Company LAND BOARDS LLC; Assembly U00; Location Rustbelt, US; Device G16V8; /* 65C816 Control */ /* Control inputs */ PIN 1 = CLK; PIN 2 = CPUA12; PIN 3 = CPUA13; PIN 4 = CPUA14; PIN 5 = CPUA15; PIN 6 = CPUREAD; PIN 8 = VPA; PIN 9 = VDA; /* Counter data inputs */ PIN 13 = !IOCS; PIN 14 = !ROMCS; PIN 15 = !MEMRD; PIN 16 = !RAMCS; PIN 18 = RDY; ROMCS = CPUA15 & CPUA14 & CPUA13 & CPUA12 & CPUREAD & VDA # CPUA15 & CPUA14 & CPUA13 & CPUA12 & CPUREAD & VPA; RAMCS = !CPUA15 & VDA # !CPUA15 & VPA; IOCS = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & VDA; MEMRD = CPUREAD & CLK; /* RDY = VPA # VDA; */