Difference between revisions of "LB-68B50-01"
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== Design == | == Design == | ||
| − | === ACIA === | + | === ACIA -Rev 2 === |
| + | |||
| + | [[file:LB-68B50-01_ACIA-Rev2.PNG]] | ||
| + | |||
| + | * 68B50 UART | ||
| + | * Baud Rate Clock (38.4k baud oscillator) | ||
| + | |||
| + | === ACIA -Rev 1 === | ||
[[file:LB-68B50-01_ACIA.PNG]] | [[file:LB-68B50-01_ACIA.PNG]] | ||
| Line 21: | Line 28: | ||
* 68B50 UART | * 68B50 UART | ||
* Baud Rate Clock (38.4k baud oscillator) | * Baud Rate Clock (38.4k baud oscillator) | ||
| + | |||
| + | === XIAO RP2040 CPU - Rev 2 === | ||
| + | |||
| + | * Fix 3.3V levels | ||
| + | |||
| + | [[file:LB-68B50-01_ACIA-Rev2.PNG]] | ||
| + | |||
| + | * USB/Serial | ||
| + | * Drive SPI I2C 8-bit parallel port expander | ||
| + | * SD card | ||
| + | |||
| + | === J4 - FTDI Header (Rev 2) === | ||
| + | |||
| + | [[file:LB-68B50-01_J4_FTDI.PNG]] | ||
| + | |||
| + | * 5V levels | ||
| + | * Pinout | ||
| + | # GND | ||
| + | # CTS (in) | ||
| + | # VCC | ||
| + | # TX (out) | ||
| + | # RX (in) | ||
| + | # RTS (out) | ||
=== XIAO RP2040 CPU - Rev 1 === | === XIAO RP2040 CPU - Rev 1 === | ||
| Line 37: | Line 67: | ||
* 3.3V levels | * 3.3V levels | ||
| + | * I2C Bus driven from RP2040 | ||
| + | * Int to RP2040 | ||
=== SD Card (Rev 2) === | === SD Card (Rev 2) === | ||
[[file:LB-68B50-01_SD_CARDL.PNG]] | [[file:LB-68B50-01_SD_CARDL.PNG]] | ||
| + | |||
| + | * Connected to RP2040 | ||
| + | * Can be used to send program code to the CPU | ||
=== SD Card (Rev1) === | === SD Card (Rev1) === | ||
| Line 69: | Line 104: | ||
=== Rev 2 === | === Rev 2 === | ||
| − | * Removed U2 voltage translator | + | [[file:LB-6850-01_FRONT_REV2(BLK).png]] |
| + | |||
| + | * Removed U2 voltage translator connections to SD Card and connect to serial lines between 5V ACIA and 3.3V RP2040 | ||
* Lift pin U1-8 | * Lift pin U1-8 | ||
* Lift pin U1-10 | * Lift pin U1-10 | ||
* Connect U1-8 to U1-10 to Vcc | * Connect U1-8 to U1-10 to Vcc | ||
| + | * Add FTDI connector | ||
=== Rev 1 === | === Rev 1 === | ||
Latest revision as of 23:03, 23 August 2024
.png)
Contents
Features
- Serial/Parallel I/O Card
- 68B50 UART
- 1.8432 MHz oscillator
- Baud Rate Clock (38.4k baud oscillator)
- XIAO RP2040 CPU
- USB/Serial
- 8-bit parallel port expander
- SD card
- 100x50mm card
Design
ACIA -Rev 2
- 68B50 UART
- Baud Rate Clock (38.4k baud oscillator)
ACIA -Rev 1
- 68B50 UART
- Baud Rate Clock (38.4k baud oscillator)
XIAO RP2040 CPU - Rev 2
- Fix 3.3V levels
- USB/Serial
- Drive SPI I2C 8-bit parallel port expander
- SD card
J4 - FTDI Header (Rev 2)
- 5V levels
- Pinout
- GND
- CTS (in)
- VCC
- TX (out)
- RX (in)
- RTS (out)
XIAO RP2040 CPU - Rev 1
- Fatal flaw, can't use the RP2040 since the UART voltages are 5V and the RP2040 doesn't work at 5V
- USB/Serial
- Drive SPI I2C 8-bit parallel port expander
- SD card
Parallel I/O Port
- 3.3V levels
- I2C Bus driven from RP2040
- Int to RP2040
SD Card (Rev 2)
- Connected to RP2040
- Can be used to send program code to the CPU
SD Card (Rev1)
- Need to not install level translators
- Need to short across the SD card lines
Backplane
Mechanicals
Rev 2
- Move J3 GND, VCC silkscreen over
Rev 1
Checkout
Rev 2
- Removed U2 voltage translator connections to SD Card and connect to serial lines between 5V ACIA and 3.3V RP2040
- Lift pin U1-8
- Lift pin U1-10
- Connect U1-8 to U1-10 to Vcc
- Add FTDI connector
Rev 1
.png)
- Do not install level translator U3
- Short across the SD card lines
- Jumper U2-13 to U2-2
- Jumper U2-12 to U2-3
- Jumper U2-11 to U2-4
- Jumper U2-10 to U2-5
- Cut etch U1-8
- Cut etch U1-10
- Add jumper U1-8 to U1-10 to U1-12
- Cut etch U1-14 (E pin of ACIA)
- Add jumper U1-14 to J1-49 (VDA)
