Difference between revisions of "LB-68B50-02"

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Line 1: Line 1:
−
[[file:LB-6850-02_P1653-720px.jpg]]
+
[[file:LB-6850-02_P1090749-720px.jpg]]
  
 
== Features ==
 
== Features ==
Line 12: Line 12:
 
== Design ==
 
== Design ==
  
−
=== ACIA ===
+
=== ACIA ===
  
 
* 68B50 UART
 
* 68B50 UART
 
* Baud Rate Clock (115,200 baud oscillator)
 
* Baud Rate Clock (115,200 baud oscillator)
  
−
[[file:LB-68B50-02_ACIA-Rev2.PNG]]
+
[[file:LB-68B50-02_ACIA_Rev2.PNG]]
  
 
=== PLD ===
 
=== PLD ===
  
 
* Customize PLD per CPU type and to match memory map
 
* Customize PLD per CPU type and to match memory map
−
* ATF16V8B part
+
** Can be used to support multiple 6850 cards
 +
* [https://www.mouser.com/ProductDetail/Microchip-Technology/ATF16V8B-15PU?qs=2mdvTlUeTfCsdBIzx6v3gA%3D%3D ATF16V8B] part
 
* [[TL866ii Plus Programmer]]
 
* [[TL866ii Plus Programmer]]
  
−
[[file:LB-68B50-02_U2_PLD.PNG]]
+
[[file:LB-68B50-02_U2_PLD_Rev2.PNG]]
  
−
==== LB-68B50-02_65CXX_PLD PLD Listing ====
+
==== LB-68B50-02_6XXX_PLD Listing ====
  
−
* 65XX specific  
+
* 6XXX (6502, 6802, 6809 specific)
  
 
<pre>
 
<pre>
−
Name      LB-68B50-02_65CXX_PLD;
+
Name      LB-68B50-02_6XXX_PLD;
 
Partno    ATF16V8B;
 
Partno    ATF16V8B;
−
Date      08/19/24;
+
Date      09/20/24;
 
Revision  01;
 
Revision  01;
 
Designer  DOUG G;
 
Designer  DOUG G;
 
Company    LAND BOARDS LLC;
 
Company    LAND BOARDS LLC;
−
Assembly  LB-68B50-02_65CXX_U2;
+
Assembly  LB-68B50-02_6XXX_U2;
 
Location  Rustbelt, US;
 
Location  Rustbelt, US;
 
Device    G16V8;
 
Device    G16V8;
  
 
/*
 
/*
−
68B50 Control for LB-65CXX-01 CPU board
+
68B50 Control for LB-6809-01, LB-6802-01, and LB-65CXX CPU boards
−
VDA is PH2OUT
+
0x8000-0xBFFF - 16KB I/O space
−
PH2OUT high during read/write cycles
 
−
0x8000-0x8FFF - 4KB I/O space
 
 
*/
 
*/
  
Line 58: Line 57:
 
PIN    7  = CPUA1;
 
PIN    7  = CPUA1;
 
PIN    8  = CPUA0;
 
PIN    8  = CPUA0;
−
PIN    9  = !IOCS;
+
PIN    9  = !IOCS; /* IOCS is IO space decoded on all CPU cards */
−
PIN    11  = VDA;
+
PIN    11  = VDA; /* Not used in any version */
−
PIN    12  = VPB;
+
PIN    12  = VPB; /* VPB is enable on 6802, 6809 AND 6502 (Rev 2 rwk) CPUs */
−
PIN    14  = !IORQ;
+
PIN    14  = !IORQ; /* IORQ* is enable on Z80 cards */
  
 
/* Address Decode and Chip Select outputs */
 
/* Address Decode and Chip Select outputs */
Line 69: Line 68:
 
PIN    19  = ACIAE;
 
PIN    19  = ACIAE;
  
−
ACIACS1 = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & IOCS & VPB;
+
ACIACS1 = CPUA15 & !CPUA14 & IOCS;
  
−
ACIACS0 = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & IOCS & VPB;
+
ACIACS0 = CPUA15 & !CPUA14 & IOCS;
  
 
ACIARS = CPUA0;
 
ACIARS = CPUA0;
  
−
ACIAE = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & IOCS & VPB;
+
ACIAE = CPUA15 & !CPUA14 & IOCS & VPB;
 
</pre>
 
</pre>
  
Line 81: Line 80:
  
 
<pre>
 
<pre>
−
Name      LB-68B50-02_PLD;
+
Name      LB-68B50-02_Z80_PLD;
 
Partno    ATF16V8B;
 
Partno    ATF16V8B;
−
Date      08/19/24;
+
Date      09/19/24;
 
Revision  01;
 
Revision  01;
 
Designer  DOUG G;
 
Designer  DOUG G;
 
Company    LAND BOARDS LLC;
 
Company    LAND BOARDS LLC;
−
Assembly  LB-685-02_U2;
+
Assembly  LB-6850-02_U2;
 
Location  Rustbelt, US;
 
Location  Rustbelt, US;
 
Device    G16V8;
 
Device    G16V8;
Line 105: Line 104:
 
PIN    8  = CPUA0;
 
PIN    8  = CPUA0;
 
PIN    9  = !IOCS;
 
PIN    9  = !IOCS;
−
PIN    11   = VDA;
+
PIN    11 = VDA;
−
PIN    12   = VPB;
+
PIN    12 = VPB;
−
PIN    14  = !IORQ;
+
PIN    13  = !IORQ;
  
 
/* Address Decode and Chip Select outputs */
 
/* Address Decode and Chip Select outputs */
Line 115: Line 114:
 
PIN    19  = ACIAE;
 
PIN    19  = ACIAE;
  
−
ACIACS1 = !CPUA1 & IOCS & IORQ;
+
ACIACS1 = IOCS & IORQ;
  
−
ACIACS0 = !CPUA1 & IOCS & IORQ;
+
ACIACS0 = IOCS & IORQ;
  
 
ACIARS = CPUA0;
 
ACIARS = CPUA0;
  
−
ACIAE = !CPUA1 & IOCS & IORQ;
+
ACIAE = IOCS & IORQ;
 
</pre>
 
</pre>
  
−
==== LB-68B50-02_6802_PLD PLD Listing ====
+
=== J2 - FTDI Header) ===
 +
 
 +
[[file:LB-68B50-02_J2_FTDI.PNG]]
  
−
<pre>
+
* 5V levels
−
Name      LB-68B50-02_68XX_PLD;
+
* Pinout
−
Partno    ATF16V8B;
+
# GND
−
Date      08/25/24;
+
# CTS (in)
−
Revision  01;
+
# VCC
−
Designer  DOUG G;
+
# TX (out)
−
Company    LAND BOARDS LLC;
+
# RX (in)
−
Assembly  LB-68B50-02_68XX_U2;
+
# RTS (out)
−
Location  Rustbelt, US;
 
−
Device    G16V8;
 
  
−
/*
+
=== Backplane ===
−
68B50 Control for LB-6809-01 and LB-6802-01 CPU boards
 
−
VDA is PH2OUT
 
−
PH2OUT high during read/write cycles
 
−
0x8000-0x8FFF - 4KB I/O space
 
−
*/
 
  
−
/* Control inputs */
+
[[file:LB-68B50-02_J1_Backplane_Rev2.PNG]]
−
PIN    1  = CPUA15;
 
−
PIN    2  = CPUA14;
 
−
PIN    3  = CPUA13;
 
−
PIN    4  = CPUA12;
 
−
PIN    5  = CPUA11;
 
−
PIN    6  = CPUA10;
 
−
PIN    7  = CPUA1;
 
−
PIN    8  = CPUA0;
 
−
PIN    9  = !IOCS; /* IOCS is IO space decoded on all CPU cards */
 
−
PIN    11  = VDA; /* VDA is PH2OUT is enable on 65CXX CPU */
 
−
PIN    12  = VPB; /* VPB is enable on 6802 and 6809 CPUs */
 
−
PIN    14  = !IORQ; /* IORQ* is enable on Z80 cards */
 
  
−
/* Address Decode and Chip Select outputs */
+
== Mechanicals ==
−
PIN    16  = ACIACS1;
 
−
PIN    17  = ACIACS0;
 
−
PIN    18  = ACIARS;
 
−
PIN    19  = ACIAE;
 
  
−
ACIACS1 = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & IOCS & VPB;
+
=== Rev 2 ===
  
−
ACIACS0 = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & IOCS & VPB;
+
[[file:LB-68B50-02_Rev2_MECHS.PNG]]
  
−
ACIARS = CPUA0;
+
=== Rev 1 ===
  
−
ACIAE = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & IOCS & VPB;
+
[[file:LB-68B50-02_Rev1_MECHS.PNG]]
−
</pre>
 
  
−
==== LB-68B50-02_6809_PLD PLD Listing ====
+
== Checkout ==
  
−
<pre>
+
=== Rev 2 Checkout ===
−
Name      LB-68B50-02_6809_PLD;
 
−
Partno    ATF16V8B;
 
−
Date      09/08/24;
 
−
Revision  01;
 
−
Designer  DOUG G;
 
−
Company    LAND BOARDS LLC;
 
−
Assembly  LB-68B50-02_6809_U2;
 
−
Location  Rustbelt, US;
 
−
Device    G16V8;
 
  
−
/*
 
−
68B50 Control for LB-6809-01 and LB-6802-01 CPU boards
 
−
VDA is PH2OUT
 
−
PH2OUT high during read/write cycles
 
−
0x8000-0x8FFF - 4KB I/O space
 
−
*/
 
  
−
/* Control inputs */
+
=== Rev 2 Changes ===
−
PIN    1  = CPUA15;
 
−
PIN    2  = CPUA14;
 
−
PIN    3  = CPUA13;
 
−
PIN    4  = CPUA12;
 
−
PIN    5  = CPUA11;
 
−
PIN    6  = CPUA10;
 
−
PIN    7  = CPUA1;
 
−
PIN    8  = CPUA0;
 
−
PIN    9  = !IOCS; /* IOCS is IO space decoded on all CPU cards */
 
−
PIN    11  = VDA; /* VDA is PH2OUT is enable on 65CXX CPU */
 
−
PIN    12  = VPB; /* VPB is Enable on 6802 and 6809 CPUs */
 
−
PIN    14  = !IORQ; /* IORQ* is enable on Z80 cards */
 
  
−
/* Address Decode and Chip Select outputs */
+
* Fixed IOCS* to be on J1-38
−
PIN    16  = ACIACS1;
+
* Fixed IORQ signal
−
PIN    17  = ACIACS0;
+
** Inv on one end but not on the other end on schematic
−
PIN    18  = ACIARS;
+
* Added config jumper J3 into PLD (U2-14) to allow for 2 configs
−
PIN    19  = ACIAE;
+
** [[LB-65CXX-01|6502]], [[LB-6802-01|6802]], [[LB-6809-01|6809]] jumper removed
 +
** [[LB-Z80-01|Z80]] jumper installed
 +
* Add LED with resistor to U2-15
 +
* Moved Osc down a bit
  
−
ACIACS1 = CPUA15 & !CPUA14 & CPUA13;
+
[[file:LB-6850-02_FRONT_REV2(BLK).png]]
  
−
ACIACS0 = CPUA15 & !CPUA14 & CPUA13;
+
=== Rev 1 Checkout ===
  
−
ACIARS = CPUA0;
+
==== IOCS* is on wrong pin ====
  
−
ACIAE = CPUA15 & !CPUA14 &  CPUA13 & !CPUA12 & IOCS & VPB;
+
* It is on J1-38 on the Rev 1 PCB
 +
* IOCS* should be on pin J1-37
 +
* Rework
 +
** Add wire J1-37 to U2-13
 +
** Cut trace near J1-38
  
−
</pre>
+
[[file:LB-68B50-02_J1-38_Rework.PNG]]
  
−
=== J2 - FTDI Header) ===
+
* Rev 1 before
  
−
[[file:LB-68B50-02_J2_FTDI.PNG]]
+
[[file:LB-68B50-02_NP_Errors-Rev2.PNG]]
  
−
* 5V levels
+
* Fixed on Rev 2 PCB
−
* Pinout
 
−
# GND
 
−
# CTS (in)
 
−
# VCC
 
−
# TX (out)
 
−
# RX (in)
 
−
# RTS (out)
 
  
−
=== Backplane ===
+
[[file:LB-68B50-02_NP_Fixed-Rev2.PNG]]
  
−
[[file:LB-68B50-01_BKPL.PNG]]
+
==== Missing IORQ signal ====
  
−
== Mechanicals ==
+
* Inverted on one end but not on the other end on schematic
 +
* Rev 1
  
−
=== Rev 1 ===
+
[[file:LB-68B50-02_U2_IORQ_Before.PNG]]
  
−
[[file:LB-68B50-02_Rev1_MECHS.PNG]]
+
* Rev 2
  
−
== Checkout ==
+
[[file:LB-68B50-02_U2_IORQ_After.PNG]]
  
−
=== Rev 1 ===
+
* Rework
 +
** Add wire U2-13 to J1-51 (Z80)
  
−
[[file:LB-6850-02_FRONT_REV1(BLK).png]]
+
== Mechanicals ==
  
−
* Missing IORQ signal. Inv on once end but not on other end
+
== Assembly Sheet ==
−
** Add wire U2-13 to J1-51 (Z80)
 
−
* IOCS* is on wrong pin (J1-37)
 
  
−
[[file:LB-68B50-02_NP_Errors-Rev2.PNG]]
+
=== Rev 2 ===
  
−
* IOCS* should be on pin (J1-38)
+
* [https://land-boards.com/LB-68B50-02/LB-68B50-02_Rev2_ibom.html Interactive BOM]
−
** Cutr trace, add wire to fix
 
−
** Fixed on Rev 2 PCB
 
  
−
== Assembly Sheet ==
+
=== Rev 1 ===
  
−
* [https://land-boards.com/LB-68B50-01/LB-68B50-02_Rev1_ibom.html Interactive BOM]
+
* [https://land-boards.com/LB-68B50-02/LB-68B50-02_Rev1_ibom.html Interactive BOM]

Latest revision as of 13:55, 16 October 2024

LB-6850-02 P1090749-720px.jpg

Features

  • Serial/Parallel I/O Card
  • 68B50 UART
  • 1.8432 MHz oscillator
    • Baud Rate Clock (115,200 baud oscillator)
  • Control PLD
  • 100x50mm card

Design

ACIA

  • 68B50 UART
  • Baud Rate Clock (115,200 baud oscillator)

LB-68B50-02 ACIA Rev2.PNG

PLD

LB-68B50-02 U2 PLD Rev2.PNG

LB-68B50-02_6XXX_PLD Listing

  • 6XXX (6502, 6802, 6809 specific)
Name       LB-68B50-02_6XXX_PLD;
Partno     ATF16V8B;
Date       09/20/24;
Revision   01;
Designer   DOUG G;
Company    LAND BOARDS LLC;
Assembly   LB-68B50-02_6XXX_U2;
Location   Rustbelt, US;
Device     G16V8;

/*
	68B50 Control for LB-6809-01, LB-6802-01, and LB-65CXX CPU boards
	0x8000-0xBFFF - 16KB I/O space
*/

/* Control inputs */
PIN    1   = CPUA15;
PIN    2   = CPUA14;
PIN    3   = CPUA13;
PIN    4   = CPUA12;
PIN    5   = CPUA11;
PIN    6   = CPUA10;
PIN    7   = CPUA1;
PIN    8   = CPUA0;
PIN    9   = !IOCS;	/* IOCS is IO space decoded on all CPU cards 	*/
PIN    11   = VDA;	/* Not used in any version	*/
PIN    12   = VPB;	/* VPB is enable on 6802, 6809 AND 6502 (Rev 2 rwk) CPUs */
PIN    14   = !IORQ;	/* IORQ* is enable on Z80 cards	*/

/* Address Decode and Chip Select outputs */
PIN    16  = ACIACS1;
PIN    17  = ACIACS0;
PIN    18  = ACIARS;
PIN    19  = ACIAE;

ACIACS1 = CPUA15 & !CPUA14 & IOCS;

ACIACS0 = CPUA15 & !CPUA14 & IOCS;

ACIARS = CPUA0;

ACIAE = CPUA15 & !CPUA14 & IOCS & VPB;

LB-68B50-02_Z80_PLD PLD Listing

Name       LB-68B50-02_Z80_PLD;
Partno     ATF16V8B;
Date       09/19/24;
Revision   01;
Designer   DOUG G;
Company    LAND BOARDS LLC;
Assembly   LB-6850-02_U2;
Location   Rustbelt, US;
Device     G16V8;

/*
	68B50 Control for Z80 CPU board
*/

/* Control inputs */
PIN    1   = CPUA15;
PIN    2   = CPUA14;
PIN    3   = CPUA13;
PIN    4   = CPUA12;
PIN    5   = CPUA11;
PIN    6   = CPUA10;
PIN    7   = CPUA1;
PIN    8   = CPUA0;
PIN    9   = !IOCS;
PIN    11  = VDA;
PIN    12  = VPB;
PIN    13  = !IORQ;

/* Address Decode and Chip Select outputs */
PIN    16  = ACIACS1;
PIN    17  = ACIACS0;
PIN    18  = ACIARS;
PIN    19  = ACIAE;

ACIACS1 = IOCS & IORQ;

ACIACS0 = IOCS & IORQ;

ACIARS = CPUA0;

ACIAE = IOCS & IORQ;

J2 - FTDI Header)

LB-68B50-02 J2 FTDI.PNG

  • 5V levels
  • Pinout
  1. GND
  2. CTS (in)
  3. VCC
  4. TX (out)
  5. RX (in)
  6. RTS (out)

Backplane

LB-68B50-02 J1 Backplane Rev2.PNG

Mechanicals

Rev 2

LB-68B50-02 Rev2 MECHS.PNG

Rev 1

LB-68B50-02 Rev1 MECHS.PNG

Checkout

Rev 2 Checkout

Rev 2 Changes

  • Fixed IOCS* to be on J1-38
  • Fixed IORQ signal
    • Inv on one end but not on the other end on schematic
  • Added config jumper J3 into PLD (U2-14) to allow for 2 configs
  • Add LED with resistor to U2-15
  • Moved Osc down a bit

LB-6850-02 FRONT REV2(BLK).png

Rev 1 Checkout

IOCS* is on wrong pin

  • It is on J1-38 on the Rev 1 PCB
  • IOCS* should be on pin J1-37
  • Rework
    • Add wire J1-37 to U2-13
    • Cut trace near J1-38

LB-68B50-02 J1-38 Rework.PNG

  • Rev 1 before

LB-68B50-02 NP Errors-Rev2.PNG

  • Fixed on Rev 2 PCB

LB-68B50-02 NP Fixed-Rev2.PNG

Missing IORQ signal

  • Inverted on one end but not on the other end on schematic
  • Rev 1

LB-68B50-02 U2 IORQ Before.PNG

  • Rev 2

LB-68B50-02 U2 IORQ After.PNG

  • Rework
    • Add wire U2-13 to J1-51 (Z80)

Mechanicals

Assembly Sheet

Rev 2

Rev 1

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