Difference between revisions of "LB-65CXX-01"

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[[file:R65C02_vs_W65C02_w65c816_Pinout_800PX.png]]
 
[[file:R65C02_vs_W65C02_w65c816_Pinout_800PX.png]]
  
−
* Pin 1 VSS/VPB
+
{| class="wikitable"
−
** GND or VPB signal name on schematic
+
! U1 Pin
−
** R65C02 - VSS (install J2:1-2)
+
! U1 Pin Name
−
** W65C02 - VPB, Vector Pull output (leave open or install J2-2-3 to route to J1-44)
+
! Sig Name
−
** W65C816 - VPB, Vector Pull output (leave open or install J2-2-3 to route to J1-44)
+
! Pullup
−
* Pin 3 PH1OUT/ABORT
+
! R65C02 sig
−
** ABORT* signal name on schematic
+
! W65C02 sig
−
** R65C02 - PH1OUT output (routes to J1-47)
+
! W65C816 sig
−
** W65C02 - PH1OUT output (routes to J1-47)
+
|-
−
** W65C816 -ABORT input (routes to J1-47) - would need to be pulled up to use
+
| 1
−
* Pin 5 NC/MLB
+
| VSS/VPB
−
** MLB signal name on schematic)
+
| J2 selects
−
** R65C02 - NC
+
| N
−
** W65C02 - MLB Memory Lock output (routes to J1-48)
+
| VSS (IN)
−
** W65C816 - MLB Memory Lock output (routes to J1-47)
+
| VPB (OUT)
−
* Pin 7 SYNC/VPA
+
| VPB (OUT)
−
** VPA signal name on schematic
+
|-
−
** R65C02 - SYNC output
+
| 3
−
** W65C02 - SYNC output
+
| PH1OUT/ABORT
−
** W65C816 - VPA Valid Program Address
+
| ABORT*
−
* Pin 35 NC/E
+
| N
−
** CPUE signal name on schematic
+
| PH1OUT (OUT)
−
** R65C02 - NC
+
| PH1OUT (OUT)
−
** W65C02 - NC
+
| ABORT (IN)
−
** W65C816 - E, Emulation or Native Mode Output (routes to J1-52)
+
|-
−
* Pin 36 NC/BE
+
| 5
−
** IORQ* signal name on schematic
+
| NC/MLB
−
** R65C02 - NC
+
| MLB
−
** W65C02 - BE, Bus Enable input (HI to enable addr/data bus)
+
| N
−
** W65C816 - BE, Bus Enable input (HI to enable addr/data bus)
+
| NC
−
* Pin 37 PH0IN/PH2IN
+
| MLB (OUT)
−
** CPUCLK signal name on schematic
+
| MLB (OUT)
−
** R65C02 - PH0IN
+
|-
−
** W65C02 - PHI2IN
+
| 7
−
** W65C816 - PHI2IN
+
| SYNC/VPA
−
* Pin 38 SO/MX
+
| VPA
−
** CPUMX signal name on schematic pulled up
+
| N
−
** R65C02 - SO* - Set overflow input
+
| SYNC (OUT)
−
** W65C02 - SOB - Set overflow input
+
| SYNC (OUT)
−
** W65C816 - MX - Memory /Index Select Status output
+
| VPA (OUT)
−
* Pin 39 PH2OUT/VDA
+
|-
−
** VDA signal name on schematic
+
| 35
−
** R65C02 - PH2OUT
+
| NC/E
−
** W65C02 - PH2OUT
+
| CPUE
−
** W65C816 - VDA
+
| N
 +
| NC
 +
| NC
 +
| EM/NAT (OUT)
 +
|-
 +
| 36
 +
| NC/BE
 +
| IORQ*
 +
| N
 +
| NC
 +
| BE (IN)
 +
| BE (IN)
 +
|-
 +
| 37
 +
| PH0IN/PH2IN
 +
| CPUCLK
 +
| N
 +
| PH0IN
 +
| PH2IN
 +
| PH2IN
 +
|-
 +
| 38
 +
| SO/MX
 +
| CPUMX
 +
| Y
 +
| SO* (IN)
 +
| SOB (IN)
 +
| MX (OUT)
 +
|-
 +
| 39
 +
| PH2OUT/VDA
 +
| VDA
 +
| N
 +
| PH2OUT (OUT)
 +
| PH2OUT (OUT)
 +
| VDA(OUT)
 +
|-
 +
|}
  
 
===== VDA/VPA (65C816) =====
 
===== VDA/VPA (65C816) =====

Revision as of 14:41, 22 August 2024

LB-65C816-01 FRONT REV1(BLK).png

Features

  • 65C02 or 65C816 CPU
  • 2 MHz (typical) Oscillator on card
  • Reset switch/power monitor
  • Address decoder PLD drives RAM/ROM/IO chip selects
  • 100x50mm card

Design

Memory Map

0x0000-0x7FFF - 32KB SRAM
0x8000-0x8FFF - 4KB I/O space
0x9000-0xBFFF - 12 KB SRAM (Using 128KB SRAM)
0xC000-0xFFFF - 16KB EPROM space

CPU

LB-65CXX-01 CPU.PNG

  • 65C02 or 65C816 CPU
  • 2 MHz
  • Install jumper J2:1-2 if CPU is not a WDC 65C02 or WDC 65C816

R65C02 vs W65C02 vs W65C816 CPUs

R65C02 vs W65C02 w65c816 Pinout 800PX.png

U1 Pin U1 Pin Name Sig Name Pullup R65C02 sig W65C02 sig W65C816 sig
1 VSS/VPB J2 selects N VSS (IN) VPB (OUT) VPB (OUT)
3 PH1OUT/ABORT ABORT* N PH1OUT (OUT) PH1OUT (OUT) ABORT (IN)
5 NC/MLB MLB N NC MLB (OUT) MLB (OUT)
7 SYNC/VPA VPA N SYNC (OUT) SYNC (OUT) VPA (OUT)
35 NC/E CPUE N NC NC EM/NAT (OUT)
36 NC/BE IORQ* N NC BE (IN) BE (IN)
37 PH0IN/PH2IN CPUCLK N PH0IN PH2IN PH2IN
38 SO/MX CPUMX Y SO* (IN) SOB (IN) MX (OUT)
39 PH2OUT/VDA VDA N PH2OUT (OUT) PH2OUT (OUT) VDA(OUT)
VDA/VPA (65C816)
  • VDA/VDA
    • 00, Internal operation (invalid address bus)
    • 01, Valid Program Address
    • 10, Valid Data Address
    • 11, Opcode-fetch

Chip Set

LB 65C02 PARTS.jpg

  • Picture shows 3 MHz CPU
  • Received 2 MHz CPU
  • As received:

SIMPLE-6502 P1090155-720px.jpg

Oscillator

LB-65CXX-01 OSC.PNG

PLD

LB-65CXX-01 PLS.PNG

PLD Listing

Name       LB-65CXX-01_PLD;
Partno     ATF16V8B;
Date       08/18/24;
Revision   01;
Designer   DOUG G;
Company    LAND BOARDS LLC;
Assembly   LB65CXX01_U2;
Location   Rustbelt, US;
Device     G16V8;

/*
	65C816 Control
*/


/* Control inputs */
PIN    1   = CLK;
PIN    2   = CPUA12;
PIN    3   = CPUA13;
PIN    4   = CPUA14;
PIN    5   = CPUA15;
PIN    6   = CPUREAD;
PIN    8   = VPA;
PIN    9   = VDA;

/* Counter data inputs */
PIN    13  = !IOCS;
PIN    14  = !ROMCS;
PIN    15  = !MEMRD;
PIN    16  = !RAMCS;
PIN    18  = RDY;

RAMCS = !CPUA15 & VDA								/* 0x0000-0x7FFF (32KB/64KB SRAM)	*/
#        CPUA15 & !CPUA14 & !CPUA13 & CPUA12 & VDA	/* 0x9000-0x9FFF (128KB SRAM)		*/
#        CPUA15 & !CPUA14 &  CPUA13 & VDA;			/* 0xA000-0xBFFF (128KB SRAM)		*/

IOCS = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & VDA;	/* 0x8000-0x8FFF (4KB space)		*/

ROMCS = CPUA15 & CPUA14 & CPUREAD & VDA;			/* 0xC000-0xFFFF (16KB space)		*/

MEMRD = CPUREAD & VDA;

/*
RDY = VPA
#     VDA;
*/

Reset Controller

LB-65CXX-01 RES.PNG

Backplane connector

LB-65CXX-01 BKPL.PNG

Mechanicals

LB-665CXX-01 REV1 MECHS.PNG

Checkout

Rev 1

  • Install jumper J2:1-2 if CPU is not a WDC 65C02 or WDC 65C816
  • IF WDC 65C02 or WDC 65C816 is used, pullup U1-36 BE input
    • NC in other CPUs

Assembly Sheet

Rev 1

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