Difference between revisions of "LB-68B50-02"
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=== Rev 1 === | === Rev 1 === | ||
| − | [[file:LB-68B50- | + | [[file:LB-68B50-02_Rev1_MECHS.PNG]] |
== Checkout == | == Checkout == | ||
Revision as of 23:58, 24 August 2024
.png)
Contents
Features
- Serial/Parallel I/O Card
- 68B50 UART
- 1.8432 MHz oscillator
- Baud Rate Clock (115,200 baud oscillator)
- Control PLD
- 100x50mm card
Design
ACIA
- 68B50 UART
- Baud Rate Clock (115,200 baud oscillator)
PLD
J2 - FTDI Header)
- 5V levels
- Pinout
- GND
- CTS (in)
- VCC
- TX (out)
- RX (in)
- RTS (out)
Backplane
Mechanicals
Rev 1
Checkout
Rev 1
