Difference between revisions of "LB-65CXX-01"

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== Assembly Sheet ==
 
== Assembly Sheet ==
 +
 +
=== Rev 2 ===
 +
 +
* [https://land-boards.com/LB-65CXX-01/LB-65CXX-01_Rev2_ibom.html Interactive BOM]
  
 
=== Rev 1 ===
 
=== Rev 1 ===
  
 
* [https://land-boards.com/LB-65CXX-01/LB-65CXX-01_Rev1_ibom.html Interactive BOM]
 
* [https://land-boards.com/LB-65CXX-01/LB-65CXX-01_Rev1_ibom.html Interactive BOM]

Revision as of 00:40, 5 September 2024

LB-65CXX-01 P1655-720px.jpg

Features

  • 65C02 or 65C816 CPU
  • 2 MHz (typical) Oscillator on card
  • Reset switch/power monitor
  • Address decoder PLD drives RAM/ROM/IO chip selects
  • 100x50mm card

Design

Memory Map

0x0000-0x7FFF - 32KB SRAM
0x8000-0x8FFF - 4KB I/O space
0x9000-0xBFFF - Free space (12 KB SRAM Using 128KB SRAM)
0xC000-0xFFFF - 16KB EPROM space

CPU

LB-65CXX-01 CPU.PNG

  • 65C02 or 65C816 CPU
    • 65C816 requires mods to the PCB (see Checkout notes below) or Rev 2 PCB
  • 2 MHz
  • Install jumper J2:1-2 if CPU is not a WDC 65C02 or WDC 65C816

R65C02 vs W65C02 vs W65C816 CPUs

U1 Pin U1 Pin Name Sig Name Pullup R65C02 sig W65C02 sig W65C816 sig
1 VSS/VPB J2 selects N VSS (IN) VPB (OUT) VPB (OUT)
3 PH1OUT/ABORT ABORT* REV2 PH1OUT (OUT) PH1OUT (OUT) ABORT (IN)
5 NC/MLB MLB N NC MLB (OUT) MLB (OUT)
7 SYNC/VPA VPA N SYNC (OUT) SYNC (OUT) VPA (OUT)
35 NC/E CPUE N NC NC EM/NAT (OUT)
36 NC/BE IORQ* REV2 NC BE (IN) BE (IN)
37 PH0IN/PH2IN CPUCLK N PH0IN PH2IN PH2IN
38 SO/MX CPUMX REV1/2 SO* (IN) SOB (IN) MX (OUT)
39 PH2OUT/VDA VDA N PH2OUT (OUT) PH2OUT (OUT) VDA (OUT)

R65C02 vs W65C02 w65c816 Pinout 800PX.png

VDA/VPA (65C816)
  • VDA/VDA
    • 00, Internal operation (invalid address bus)
    • 01, Valid Program Address
    • 10, Valid Data Address
    • 11, Opcode-fetch

Chip Set

LB 65C02 PARTS.jpg

  • Picture shows 3 MHz CPU
  • Received 2 MHz CPU
  • As received:

SIMPLE-6502 P1090155-720px.jpg

Oscillator

LB-65CXX-01 OSC.PNG

PLD

LB-65CXX-01 PLS.PNG

PLD Listing

Name       LB-65CXX-01_PLD;
Partno     ATF16V8B;
Date       08/19/24;
Revision   01;
Designer   DOUG G;
Company    LAND BOARDS LLC;
Assembly   LB65CXX01_U2;
Location   Rustbelt, US;
Device     G16V8;

/*
	65C816 Control
*/

/* Control inputs */
PIN    1   = CLK;
PIN    2   = CPUA12;
PIN    3   = CPUA13;
PIN    4   = CPUA14;
PIN    5   = CPUA15;
PIN    6   = CPUREAD;
PIN    8   = VPA;
PIN    9   = VDA;		/* Pin 39, PH2OUT - Enable line */

/* Address Decode and Chip Select outputs */
PIN    13  = !IOCS;
PIN    14  = !ROMCS;
PIN    15  = !MEMRD;
PIN    16  = !RAMCS;
PIN    18  = RDY;

RAMCS = !CPUA15 & VDA								/* 0x0000-0x7FFF (32KB/64KB SRAM)	*/
#        CPUA15 & !CPUA14 & !CPUA13 & CPUA12 & VDA	/* 0x9000-0x9FFF (128KB SRAM)		*/
#        CPUA15 & !CPUA14 &  CPUA13 & VDA;			/* 0xA000-0xBFFF (128KB SRAM)		*/

IOCS = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & VDA;	/* 0x8000-0x8FFF (4KB space)		*/

ROMCS = CPUA15 & CPUA14 & CPUREAD & VDA;			/* 0xC000-0xFFFF (16KB space)		*/

MEMRD = !CPUA15 &                              CPUREAD & VDA	/* 0x0000-0x7FFF		*/
#        CPUA15 & !CPUA14 & !CPUA13 & CPUA12 & CPUREAD & VDA	/* 0x9000-0x9FFF		*/
#        CPUA15 & !CPUA14 &  CPUA13 &          CPUREAD & VDA	/* 0xA000-0xBFFF		*/
#        CPUA15 &  CPUA14 &                    CPUREAD & VDA;	/* 0xC000-0xFFFF		*/

/*
RDY = VDA;
*/

Reset Controller

LB-65CXX-01 RES.PNG

Backplane connector

LB-65CXX-01 BKPL.PNG

Software

Mechanicals

LB-665CXX-01 REV2 MECHS.PNG

Checkout

Rev 2

Rev 2 Checkout

Rev 2 Changes

  • Add pull-up resistor on ABORT* line (U1-3)
  • Add pull-up resistor on BE line (U1-36)

LB-65CXX-01 CPU Rev2.PNG

Rev 1

  • Install jumper J2:1-2 if CPU is not a WDC 65C02 or WDC 65C816
  • If WDC 65C02 or WDC 65C816 is used:
    • Add pull-up resistor on ABORT* line (U1-3)
    • Add pull-up resistor on BE line (U1-36)

Assembly Sheet

Rev 2

Rev 1