Difference between revisions of "LB-Z80-01"

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Line 59: Line 59:
 
Name      LB-Z80-01_PLD;
 
Name      LB-Z80-01_PLD;
 
Partno    ATF16V8B;
 
Partno    ATF16V8B;
Date      09/17/20;
+
Date      10/14/24;
Revision  01;
+
Revision  02;
 
Designer  DOUG G;
 
Designer  DOUG G;
 
Company    LAND BOARDS LLC;
 
Company    LAND BOARDS LLC;
Line 67: Line 67:
 
Device    G16V8;
 
Device    G16V8;
  
/*
+
/* Rev 2 PCB
 
*/
 
*/
  
Line 81: Line 81:
 
PIN    8  = !CPURD;
 
PIN    8  = !CPURD;
 
PIN    9  = !CPUWR;
 
PIN    9  = !CPUWR;
 +
PIN    11  = CPUD0;
  
 
/* Address Decode and Chip Select outputs */
 
/* Address Decode and Chip Select outputs */
 
PIN    13  = !ROMCS;
 
PIN    13  = !ROMCS;
 
PIN    14  = !IOCS;
 
PIN    14  = !IOCS;
 +
PIN    15  = !RAMCS;
 
PIN    16  = !MEMRD;
 
PIN    16  = !MEMRD;
PIN    15 = !RAMCS;
+
/* PIN    17 = !WAIT; */
PIN    18  = !WAIT;
+
PIN    18  = LED;
  
 
ROMCS = !CPUA15 & !CPUA14 & !CPUA13 & MREQ & CPURD;
 
ROMCS = !CPUA15 & !CPUA14 & !CPUA13 & MREQ & CPURD;
  
 +
/* 56KB SRAM */
 +
/*
 
RAMCS = CPUA15 & MREQ
 
RAMCS = CPUA15 & MREQ
 
#      CPUA14 & MREQ
 
#      CPUA14 & MREQ
 
#      CPUA13 & MREQ;
 
#      CPUA13 & MREQ;
 +
*/
 +
 +
/* 32KB SRAM */
 +
RAMCS = CPUA15 & MREQ;
  
 
IOCS = !M1 & IORQ;
 
IOCS = !M1 & IORQ;
  
 +
/*
 
WAIT = !MREQ # !IORQ;
 
WAIT = !MREQ # !IORQ;
 +
*/
  
 
MEMRD = CPURD;
 
MEMRD = CPURD;
 +
 +
LED =    !CPUA15 & !CPUA14 & !CPUA13 & MREQ & CPUWR & CPUD0
 +
# LED & !(!CPUA15 & !CPUA14 & !CPUA13 & MREQ & CPUWR);
 +
 
</pre>
 
</pre>
  

Revision as of 20:28, 14 October 2024

LB-Z80 P1090715-720px.jpg

Features

  • Z80 CPU
  • Oscillator 8 MHz nominal on card
  • Reset switch/power monitor
  • Address decoder PLD drives RAM/ROM/IO chip selects
  • 100x50mm card

Memory Map

  • 0x0000-0x1FFF 8KB ROM
  • 32KB or 56KB SRAM
    • 0x8000-0xFFFF Using LB-MEM-02 has 32 KB SRAM
    • 0x2000-0xFFFF Using LB-MEM-04 has 128KB or 512 KB of SRAM so 56 KB can be available
  • I/O
    • 0x00-0x7F - Free
    • 0x80-0x81 - Serial port (ACIA)

Design

CPU and Power Supervisor/Reset

LB-Z80-01 CPU Rev2.PNG

  • Z80 CPU
  • Oscillator 8 MHz nominal on card
  • Reset switch/power monitor

Z80 Register Set

Z80 Registers.PNG

Memory Access Timing

Z80 Mem Rd Wr.PNG

I/O Access Timing

Z80 IO Rd Wr.PNG

Oscillator

LB-Z80-01 OSC.PNG

  • 8MHZ or 10 MHz oscillator

PLD

LB-Z80-01 PLD Rev2.PNG

PLD Listing

Name       LB-Z80-01_PLD;
Partno     ATF16V8B;
Date       10/14/24;
Revision   02;
Designer   DOUG G;
Company    LAND BOARDS LLC;
Assembly   LB-Z80-01_U2;
Location   Rustbelt, US;
Device     G16V8;

/* Rev 2 PCB
*/


/* Control inputs */
PIN    1   = CLK;
PIN    2   = CPUA13;
PIN    3   = CPUA14;
PIN    4   = CPUA15;
PIN    5   = !MREQ;
PIN    6   = !IORQ;
PIN    7   = !M1;
PIN    8   = !CPURD;
PIN    9   = !CPUWR;
PIN    11  = CPUD0;

/* Address Decode and Chip Select outputs */
PIN    13  = !ROMCS;
PIN    14  = !IOCS;
PIN    15  = !RAMCS;
PIN    16  = !MEMRD;
/* PIN    17  = !WAIT; */
PIN    18  = LED;

ROMCS = !CPUA15 & !CPUA14 & !CPUA13 & MREQ & CPURD;

/* 56KB SRAM */
/*
RAMCS = CPUA15 & MREQ
#       CPUA14 & MREQ
#       CPUA13 & MREQ;
*/

/* 32KB SRAM */
RAMCS = CPUA15 & MREQ;

IOCS = !M1 & IORQ;

/*
WAIT = !MREQ # !IORQ;
*/

MEMRD = CPURD;

LED =     !CPUA15 & !CPUA14 & !CPUA13 & MREQ & CPUWR & CPUD0
# LED & !(!CPUA15 & !CPUA14 & !CPUA13 & MREQ & CPUWR);

Backplane Connector

LB-Z80-01 BKPL.PNG

Software

Assembly Language Toolchain

ACIA Loopback Test Code

  • AciaTest.asm - Source code
  • Type a character, get it back
    • 115,200 baud, 1 stop bit, no parity
  • Works

String Test Code

  • StringTest.asm - Source code
  • String write code
  • Includes loopback code
  • Works

String Read/Interpreter Code

  • ReadStringTest.asm - Source code
  • Adds a string read function
  • Adds an interpreter skeleton
  • Works with Rev 1 card
  • Works with Rev 2 card

NASCOM 2 BASIC

NASCOM BOOT.PNG

Short Test Program

10 I=0
20 PRINTI:I=I+1:GOTO 20

Build Details

  • TASM assembler (see above)
  • S Record and Hex file manipulation
  • Adds srec_cat to combine files into one Intel Hex file
    • Combine int32k.hex and BAS32K.HEX into rom32.hex using srec-cat
    • Command line
      • srec_cat.exe int32k.hex -Intel BAS32K.HEX -Intel -fill 0xff 0x0144 0x014f -o rom32.hex -Intel
  • _ASSEMBLE.BAT - double-click in Windows to run the assembly if needed

NASCOM BASIC - Code Repository

Source files

  • intmini.asm - the interupt driven mini startup program needed to boot into BASIC
  • basic.asm - BASIC 4.7b - a conversion of Microsoft BASIC 4.7, as used on the Nascom computers (see below for details)

Output files

  • List files
    • INTMINI.LST
    • BASIC.LST
  • Hex files
    • INTMINI.HEX
    • BASIC.HEX
    • ROM32.HEX - the complete 8K ROM ready for burning to an EPROM
      • The unused contents are filled with FF values.
      • Within the ROM, the serial handler is first (starting at address 0000H), followed by the BASIC interpreter (starting at 0100H).
  • Hex file format

IntelHexRecordFormat.png

  • ASCII Table

ASCII TABLE.PNG

Acknowledgements

  • BASIC is Microsoft BASIC 4.7 for the NASCOM, heavily modified by Grant to remove references to different monitors, screen handlers and keyboard matrix reading
  • TASM assembler is a partial distribution of the package from Speech Technology Incorporated

References

ASCII TABLE.PNG

Mechanicals

Rev 2 Mechanicals

LB-Z80-01 MECH Rev2.PNG

Rev 1 Mechanicals

LB-Z80-01 MECH.PNG

Checkout

Rev 2 Changes

  • Fixed resistor silkscreen values
  • Re-sequenced resistor reference designator
  • Made reset switch right angle
  • Add LED and resistor to PLD pin 15
  • Add CPUD0 to PLD pin 11
  • Added bulk capacitor

LB-Z80-01 FRONT-Rev-2 3D.png

Rev 1 Checkout

  • Didn't use silkscreen values, used
    • R1 = 4.7K
    • Other resistors are 10K
  • Z80 nop tester nop = 0x00
    • Refresh complicates this
  • Made C2 a bulk cap (100uF)

Assembly Sheet