Difference between revisions of "LB-65CXX-01"

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Line 18: Line 18:
 
* 2 MHz
 
* 2 MHz
  
==== R65C02 vs W65C92 CPUs ====
+
==== R65C02 vs W65C02 CPUs ====
  
 
[[file:R65C02_vs_W65C02Pinout.png]]
 
[[file:R65C02_vs_W65C02Pinout.png]]
  
* Pin differences
+
* R65C02 vs W65C02 pin differences
 
** Pin 1
 
** Pin 1
 
*** R65C02 = VSS J2:1-2
 
*** R65C02 = VSS J2:1-2

Revision as of 20:07, 18 August 2024

LB-65C816-01 FRONT REV1(BLK).png

Features

  • 65C02 or 65C816 CPU
  • 2 MHz Oscillator on card
  • Reset switch/power monitor
  • Address decoder PLD drives RAM/ROM/IO chip selects
  • 100x50mm card

Design

CPU

LB-65CXX-01 CPU.PNG

  • 65C02 or 65C816 CPU
  • 2 MHz

R65C02 vs W65C02 CPUs

R65C02 vs W65C02Pinout.png

  • R65C02 vs W65C02 pin differences
    • Pin 1
      • R65C02 = VSS J2:1-2
      • W65C02 = VPB J2:2-3 - Vector Pull
    • Pin 5
      • R65C02 = NC
      • W65C02 = MLB - Memory Lock
    • Pin 36
      • R65C02 = NC
      • W65C02 = BE - Bus Enable

Oscillator

LB-65CXX-01 OSC.PNG

PLD

LB-65CXX-01 PLS.PNG

Name       LB-65CXX-01_PLD;
Partno     ATF16V8B;
Date       09/09/20;
Revision   01;
Designer   DOUG G;
Company    LAND BOARDS LLC;
Assembly   U00;
Location   Rustbelt, US;
Device     G16V8;

/*
	65C816 Control
*/


/* Control inputs */
PIN    1   = CLK;
PIN    2   = CPUA12;
PIN    3   = CPUA13;
PIN    4   = CPUA14;
PIN    5   = CPUA15;
PIN    6   = CPUREAD;
PIN    8   = VPA;
PIN    9   = VDA;

/* Counter data inputs */
PIN    13  = !IOCS;
PIN    14  = !ROMCS;
PIN    15  = !MEMRD;
PIN    16  = !RAMCS;
PIN    18  = RDY;

ROMCS = CPUA15 & CPUA14 & CPUA13 & CPUA12 & CPUREAD & VDA
#       CPUA15 & CPUA14 & CPUA13 & CPUA12 & CPUREAD & VPA;

RAMCS = !CPUA15 & VDA
#       !CPUA15 & VPA;

IOCS = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & VDA;

MEMRD = CPUREAD & CLK;

/*
RDY = VPA
#     VDA;
*/

Reset Controller

LB-65CXX-01 RES.PNG

Backplane connector

LB-65CXX-01 BKPL.PNG