Difference between revisions of "LB-Z80-01"
Jump to navigation
Jump to search
Blwikiadmin (talk | contribs) |
Blwikiadmin (talk | contribs) |
||
| Line 8: | Line 8: | ||
* Address decoder PLD drives RAM/ROM/IO chip selects | * Address decoder PLD drives RAM/ROM/IO chip selects | ||
* 100x50mm card | * 100x50mm card | ||
| + | |||
| + | === Memory Map === | ||
| + | |||
| + | * 0x0000-0x1FFF 8KB ROM | ||
| + | * 0x2000-0xFFFF 56KB SRAM | ||
| + | * I/O | ||
| + | ** 0x00-0x7F - Free | ||
| + | ** 0x80-0x81 - Serial port (ACIA) | ||
== Design == | == Design == | ||
Revision as of 13:46, 19 August 2024
Contents
Features
- Z80 CPU
- Oscillator 8 MHz nominal on card
- Reset switch/power monitor
- Address decoder PLD drives RAM/ROM/IO chip selects
- 100x50mm card
Memory Map
- 0x0000-0x1FFF 8KB ROM
- 0x2000-0xFFFF 56KB SRAM
- I/O
- 0x00-0x7F - Free
- 0x80-0x81 - Serial port (ACIA)
Design
CPU and Power Supervisor/Reset
Oscillator
PLD
PLS Listing
Backplane Connector
Mechanicals
