Difference between revisions of "LB-68B50-02"
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* Baud Rate Clock (115,200 baud oscillator) | * Baud Rate Clock (115,200 baud oscillator) | ||
| − | [[file:LB-68B50-02_ACIA.PNG]] | + | [[file:LB-68B50-02_ACIA-Rev1.PNG]] |
=== J2 - FTDI Header (Rev 2) === | === J2 - FTDI Header (Rev 2) === | ||
Revision as of 23:50, 24 August 2024
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Contents
Features
- Serial/Parallel I/O Card
- 68B50 UART
- 1.8432 MHz oscillator
- Baud Rate Clock (115,200 baud oscillator)
- Control PLD
- 100x50mm card
Design
ACIA
- 68B50 UART
- Baud Rate Clock (115,200 baud oscillator)
J2 - FTDI Header (Rev 2)
- 5V levels
- Pinout
- GND
- CTS (in)
- VCC
- TX (out)
- RX (in)
- RTS (out)
Backplane
Mechanicals
Rev 2
- Move J3 GND, VCC silkscreen over
Rev 1
Checkout
Rev 1
