Difference between revisions of "LB-68B50-02"

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[[file:LB-68B50-02_ACIA-Rev1.PNG]]
 
[[file:LB-68B50-02_ACIA-Rev1.PNG]]
  
−
=== J2 - FTDI Header (Rev 2) ===
+
=== J2 - FTDI Header) ===
  
−
[[file:LB-68B50-01_J4_FTDI.PNG]]
+
[[file:LB-68B50-02_J2_FTDI.PNG]]
  
 
* 5V levels
 
* 5V levels

Revision as of 23:51, 24 August 2024

LB-6850-02 FRONT REV1(BLK).png

Features

  • Serial/Parallel I/O Card
  • 68B50 UART
  • 1.8432 MHz oscillator
    • Baud Rate Clock (115,200 baud oscillator)
  • Control PLD
  • 100x50mm card

Design

ACIA

  • 68B50 UART
  • Baud Rate Clock (115,200 baud oscillator)

LB-68B50-02 ACIA-Rev1.PNG

J2 - FTDI Header)

LB-68B50-02 J2 FTDI.PNG

  • 5V levels
  • Pinout
  1. GND
  2. CTS (in)
  3. VCC
  4. TX (out)
  5. RX (in)
  6. RTS (out)

Backplane

LB-68B50-01 BKPL.PNG

Mechanicals

Rev 2

LB-68B50-01 Rev2 MECHS.PNG

  • Move J3 GND, VCC silkscreen over

Rev 1

File:LB-68B50-02 MECHS.PNG

Checkout

Rev 1

LB-6850-02 FRONT REV1(BLK).png

Assembly Sheet

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