Difference between revisions of "LB-Z80-01"

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=== Rev 1 ===
 
=== Rev 1 ===
 +
 +
* [LB-BKOUT-01#NOP_Tester nop tester] Z80 nop = 0x00
  
 
== Assembly Sheet ==
 
== Assembly Sheet ==
  
 
* [https://land-boards.com/LB-Z80-01/LB-Z80-01_Rev1_ibom.html Interactive BOM]
 
* [https://land-boards.com/LB-Z80-01/LB-Z80-01_Rev1_ibom.html Interactive BOM]

Revision as of 13:25, 4 September 2024

LB-Z80-01 P1658-720px.jpg

Features

  • Z80 CPU
  • Oscillator 8 MHz nominal on card
  • Reset switch/power monitor
  • Address decoder PLD drives RAM/ROM/IO chip selects
  • 100x50mm card

Memory Map

  • 0x0000-0x1FFF 8KB ROM
  • 0x2000-0xFFFF 56KB SRAM
    • LB-MEM-02 has 32 KB ARAM w/ 24KB
    • LB-MEM-03 has 128KB or 512 KB of SRAM so 56 KB can be available
  • I/O
    • 0x00-0x7F - Free
    • 0x80-0x81 - Serial port (ACIA)

Design

CPU and Power Supervisor/Reset

LB-Z80-01 CPU.PNG

  • Z80 CPU
  • Oscillator 8 MHz nominal on card
  • Reset switch/power monitor

Oscillator

LB-Z80-01 OSC.PNG

  • 8MHZ or 10 MHz oscillator

PLD

LB-Z80-01 PLD.PNG

PLD Listing

Name       LB-Z80-01_PLD;
Partno     ATF16V8B;
Date       09/17/20;
Revision   01;
Designer   DOUG G;
Company    LAND BOARDS LLC;
Assembly   LB-Z80-01_U2;
Location   Rustbelt, US;
Device     G16V8;

/*
*/


/* Control inputs */
PIN    1   = CLK;
PIN    2   = CPUA13;
PIN    3   = CPUA14;
PIN    4   = CPUA15;
PIN    5   = !MREQ;
PIN    6   = !IORQ;
PIN    7   = !M1;
PIN    8   = !CPURD;
PIN    9   = !CPUWR;

/* Address Decode and Chip Select outputs */
PIN    13  = !ROMCS;
PIN    14  = !IOCS;
PIN    16  = !MEMRD;
PIN    15  = !RAMCS;
PIN    18  = !WAIT;

ROMCS = !CPUA15 & !CPUA14 & !CPUA13 & MREQ & CPURD;

RAMCS = CPUA15 & MREQ
#       CPUA14 & MREQ
#       CPUA13 & MREQ;

IOCS = !M1 & IORQ;

WAIT = !MREQ # !IORQ;

MEMRD = CPURD;

Backplane Connector

LB-Z80-01 BKPL.PNG

Software

Mechanicals

LB-Z80-01 MECH.PNG

Checkout

Rev 1

  • [LB-BKOUT-01#NOP_Tester nop tester] Z80 nop = 0x00

Assembly Sheet