LB-65CXX-01

Features

• 65C02 or 65C816 CPU
• 2 MHz (typical) Oscillator on card
• Reset switch/power monitor
• Address decoder PLD drives RAM/ROM/IO chip selects
• 100x50mm card

Design

Memory Map

0x0000-0x7FFF - 32KB SRAM
0x8000-0x8FFF - 4KB I/O space
0x9000-0xBFFF - 12 KB SRAM (Using 128KB SRAM)
0xC000-0xFFFF - 16KB EPROM space

CPU

• 65C02 or 65C816 CPU
• 2 MHz
• Install jumper J2:1-2 if CPU is not a WDC 65C02 or WDC 65C816

R65C02 vs W65C02 vs W65C816 CPUs

• Pin 1 VSS/VPB
  • GND or VPB signal name on schematic
  • R65C02 - VSS (install J2:1-2)
  • W65C02 - VPB, Vector Pull output (install J2-2-3 to route to J1-44)
  • W65C816 - VPB, Vector Pull output (install J2-2-3 to route to J1-44)
• Pin 3 PH1OUT/ABORT
  • ABORT* signal name on schematic
  • R65C02 - PH1OUT output (routes to J1-47)
  • W65C02 - PH1OUT output (routes to J1-47)
  • W65C816 -ABORT input (routes to J1-47)
• Pin 5 NC/MLB
  • MLB signal name on schematic)
  • R65C02 - NC
  • W65C02 - MLB Memory Lock output (routes to J1-48)
  • W65C816 - MLB Memory Lock output (routes to J1-47)
• Pin 7 SYNC/VPA
  • VPA signal name on schematic
  • R65C02 - SYNC output
  • W65C02 - SYNC output
  • W65C816 - VPA Valid Program Address
• Pin 35 NC/E
  • CPUE signal name on schematic
  • R65C02 - NC
  • W65C02 - NC
  • W65C816 - E, Emulation or Native Mode Output (routes to J1-52)
• Pin 36 NC/BE
  • IORQ* signal name on schematic
  • R65C02 - NC
  • W65C02 - BE, Bus Enable input (HI to enable addr/data bus)
  • W65C816 - BE, Bus Enable input (HI to enable addr/data bus)
• Pin 37 PH0IN/PH2IN
  • CPUCLK signal name on schematic
  • R65C02 - PH0IN
  • W65C02 - PHI2IN
  • W65C816 - PHI2IN
• Pin 38 SOB/MX
  • CPUMX signal name on schematic pulled up
  • R65C02 - SO* - Set overflow input
  • W65C02 - SOB - Set overflow input
  • W65C816 - MX - Memory /Index Select Status output
• Pin 39 PH2OUT/VDA
  • VDA signal name on schematic
  • R65C02 - PH2OUT
  • W65C02 - PH2OUT
  • W65C816 - VDA

VDA/VPA (65C816)

• VDA/VDA
  • 00, Internal operation (invalid address bus)
  • 01, Valid Program Address
  • 10, Valid Data Address
  • 11, Opcode-fetch

Chip Set

• Ordered from Ebay

• Picture shows 3 MHz CPU
• Received 2 MHz CPU
• As received:

Oscillator

PLD

PLD Listing

Name       LB-65CXX-01_PLD;
Partno     ATF16V8B;
Date       08/18/24;
Revision   01;
Designer   DOUG G;
Company    LAND BOARDS LLC;
Assembly   LB65CXX01_U2;
Location   Rustbelt, US;
Device     G16V8;

/*
	65C816 Control
*/


/* Control inputs */
PIN    1   = CLK;
PIN    2   = CPUA12;
PIN    3   = CPUA13;
PIN    4   = CPUA14;
PIN    5   = CPUA15;
PIN    6   = CPUREAD;
PIN    8   = VPA;
PIN    9   = VDA;

/* Counter data inputs */
PIN    13  = !IOCS;
PIN    14  = !ROMCS;
PIN    15  = !MEMRD;
PIN    16  = !RAMCS;
PIN    18  = RDY;

RAMCS = !CPUA15 & VDA								/* 0x0000-0x7FFF (32KB/64KB SRAM)	*/
#        CPUA15 & !CPUA14 & !CPUA13 & CPUA12 & VDA	/* 0x9000-0x9FFF (128KB SRAM)		*/
#        CPUA15 & !CPUA14 &  CPUA13 & VDA;			/* 0xA000-0xBFFF (128KB SRAM)		*/

IOCS = CPUA15 & !CPUA14 & !CPUA13 & !CPUA12 & VDA;	/* 0x8000-0x8FFF (4KB space)		*/

ROMCS = CPUA15 & CPUA14 & CPUREAD & VDA;			/* 0xC000-0xFFFF (16KB space)		*/

MEMRD = CPUREAD & VDA;

/*
RDY = VPA
#     VDA;
*/

Reset Controller

• DS1813-5 Reset Controller
• 5V Power Monitor
• Reset controller
• Reset pushbutton to ground

Backplane connector

Mechanicals

Checkout

Rev 1

• Install jumper J2:1-2 if CPU is not a WDC 65C02 or WDC 65C816
• IF WDC 65C02 or WDC 65C816 is used, pullup U1-36 BE input
  • NC in other CPUs

Assembly Sheet

Rev 1

• Interactive BOM