IOP16 UART
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Contents
UART and Baud Rate Generator
UART Programming Interface
- Interface mimics ACIA software interface address/control/status contents
- Two addresses, Control/status and data access
Status Register (Read)
- Register Select = 0
- Bits
d0 = RDRF = Receive Data Register Full (1 = data is ready to read) d1 = TDRE = Transmit Data Register Empty (1 = transmit is ready to send out data) d2 = DCD = Data Carrier Detect (0 = carrier present - hardwired) d3 = CTS = Clear to Send (0 = Clear to Send - ready to accept data - hardwired) d7 = IRQ = Interrupt Request (1 = Interrupt present)
Control Register (Write)
- Register Select = 0
- Bits
d1,d0 = Control (11 = Master Reset) d6,d5 = TC = Transmitter Control (RTS = Transmitter Interrupt Enable/Disable) d7 = Interrupt Enable (1=enable interrupts)
Data Register (Read/Write)
- Register Select = 1
- Read = Read data from the data register (not implemented due to kbd removal)
- Write = Write data to the data register
Baud Rate Generator for buffered UART
- Assumes 50 MHz clock
- Pass Baud Rate in BAUD_RATE generic as integer value (300, 9600, 115,200)
- Legal values are 115200, 38400, 19200, 9600, 4800, 2400, 1200, 600, 300
- Call with
BaudRateGen : entity work.BaudRate6850 GENERIC map ( BAUD_RATE => 115200 ) PORT map ( i_CLOCK_50 => i_CLOCK_50, o_serialEn => serialEn );