Difference between revisions of "R32V2020 Peripheral Interfaces"

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** 50 MHz clock
 
** 50 MHz clock
 
** 56 of 1K BlockRAM (EP4CE15)
 
** 56 of 1K BlockRAM (EP4CE15)
* [http://land-boards.com/blwiki/index.php?title=RETRO-EP4 Land Boards RETRO-EP4] Card
+
* [[RETRO-EP4|Land Boards RETRO-EP4]] Card
 
** Mounts [https://www.waveshare.com/wiki/CoreEP4CE6 WaveShare Altera Cyclone IV EP4CE6 FPGA board]
 
** Mounts [https://www.waveshare.com/wiki/CoreEP4CE6 WaveShare Altera Cyclone IV EP4CE6 FPGA board]
 
** 50 MHz clock
 
** 50 MHz clock
 
** 30 of 1K BlockRAM
 
** 30 of 1K BlockRAM
* Purchased [http://land-boards.com/blwiki/index.php?title=A-C4E6_Cyclone_IV_FPGA_EP4CE6E22C8N_Development_Board Altera EP4CE6 FPGA board]
+
* Purchased [[A-C4E6_Cyclone_IV_FPGA_EP4CE6E22C8N_Development_Board|Altera EP4CE6 FPGA board]]]
 
** 50 MHz clock
 
** 50 MHz clock
 
** 30 of 1K BlockRAM
 
** 30 of 1K BlockRAM
* Purchased [http://land-boards.com/blwiki/index.php?title=A-C4E10_Cyclone_IV_FPGA_EP4CE10E22C8N_Development_Board Altera EP4CE10 FPGA board]
+
* Purchased [[A-C4E10_Cyclone_IV_FPGA_EP4CE10E22C8N_Development_Board|Altera EP4CE10 FPGA board]]
 
** 50 MHz clock
 
** 50 MHz clock
 
** 46 of 1K BlockRAM
 
** 46 of 1K BlockRAM
* Purchased [http://land-boards.com/blwiki/index.php?title=A-ESTF_V2_EP4CE22_Board Altera EP4CE22 FPGA Board]
+
* Purchased [[A-ESTF_V2_EP4CE22_Board|Altera EP4CE22 FPGA Board]]
 
** 50 MHz clock
 
** 50 MHz clock
 
** 66 of 1K BlockRAM
 
** 66 of 1K BlockRAM

Revision as of 12:29, 10 April 2022

This is the Peripheral hardware that has been tested with the Multicomp project

FPGA Cards

Tested Peripheral Interfaces

Not all of the above cards have support for the following.

Peripheral Data Sizes

  • Peripherals can be byte, short, or long sized
  • Byte devices connect to d0-d7
  • Short devices connect to d0-d15
  • Long devices connect to d0-d31

Peripheral Memory Map