Difference between revisions of "IOP16 16-bit I/O CPU Design"
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=== Target Hardware === | === Target Hardware === | ||
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* The initial targeted hardware is the [[QMTECH_EP4CE15_FPGA_Starter_Kit|QMTECH EP4CE15 FPGA Starter Kit card]] | * The initial targeted hardware is the [[QMTECH_EP4CE15_FPGA_Starter_Kit|QMTECH EP4CE15 FPGA Starter Kit card]] | ||
** This FPGA is inexpensive and powerful | ** This FPGA is inexpensive and powerful | ||
** The CPU takes up very little of the resources of the FPGA | ** The CPU takes up very little of the resources of the FPGA | ||
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* [https://github.com/ChinaQMTECH/CYCLONE_IV_STARTER_KIT QMTECH CYCLONE IV STARTER KIT GitHub] | * [https://github.com/ChinaQMTECH/CYCLONE_IV_STARTER_KIT QMTECH CYCLONE IV STARTER KIT GitHub] | ||
** [https://github.com/douggilliland/FPGA_Cards/tree/master/QMTECH_CYCLONE_IV_STARTER_KIT QMTECH FPGA Files Reflector] | ** [https://github.com/douggilliland/FPGA_Cards/tree/master/QMTECH_CYCLONE_IV_STARTER_KIT QMTECH FPGA Files Reflector] | ||
* [https://www.aliexpress.com/item/33007471265.html?spm=a2g0o.store_pc_groupList.8148356.5.2f5a77a2912sNP QMTECH EP4CE15 FPGA card] - AliExpress page | * [https://www.aliexpress.com/item/33007471265.html?spm=a2g0o.store_pc_groupList.8148356.5.2f5a77a2912sNP QMTECH EP4CE15 FPGA card] - AliExpress page | ||
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| + | <video type="youtube">02s5rlaEy4Q</video> | ||
== Peripheral Support == | == Peripheral Support == | ||
Revision as of 15:14, 10 April 2022
Contents
Overview
This CPU is intended to be used as an I/O Processor. The CPU can be used as a Microcontroller replacement in many applications. It implemented in an FPGA. It is useful for offloading polled I/O or replacing CPUs in small applications. The majority of these applications deal with 8-bit data and that's where this CPU excels.
Features Set
- 16-bit CPU
- Simple/consistent opcode bit fields
- Instructions are always only 16-bits wide
- 4-bit opcode
- Some sub-instructions allow more than 16 instructions
- 4-bit register field (shared with address/offset)
- 8-bit constant (shared with address/offset)
- High enough Performance - 12.5 MIPS (4 of 50 MHz FPGA clocks)
- Register File
- 8 General Purpose registers
- 3 constant value registers
- Registers are 8-bits
- 12-bit of Program address (up to 4K instructions)
- Return Stack - 1 deep or optionally deeper as build option
IOP16 Block Diagram
Instruction Set
Assembler
- Table driven Assembler
- Input comes from a CSV file
- Outputs .MIF and Listing files
- MIF (Memory Initialization File) is Altera ROM initialization File
Hardware Requirements
- Targeted at an FPGA implementation
- The CPU could easily be run on pretty much any FPGA
- Coded in VHDL
- Very small LUT/Memory footprint in FPGA
- Uses 226 logic cells in an Altera EP4 FPGA
- Requires a minimum 2 of 1K SRAM blocks (depends on program size)
- Trade-off - SRAM could be replaced with logic cells (in theory)
Target Hardware
- The initial targeted hardware is the QMTECH EP4CE15 FPGA Starter Kit card
- This FPGA is inexpensive and powerful
- The CPU takes up very little of the resources of the FPGA
- QMTECH CYCLONE IV STARTER KIT GitHub
- QMTECH EP4CE15 FPGA card - AliExpress page
Peripheral Support
- Extensive Peripheral Support
- 8-bit address (controls up to 256 peripherals)
- 8-bit data
- Read strobe (a couple of clocks wide)
- Write strobe (a couple of clocks wide)
