Difference between revisions of "IOP16 16-bit I/O CPU Design"

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[https://www.youtube.com/watch?v=ZtEJHF-pVU0&list=PLn__0BqzWEWNspQ0xkG5h-oSJ21EAet8H Video PlayList]
 
[https://www.youtube.com/watch?v=ZtEJHF-pVU0&list=PLn__0BqzWEWNspQ0xkG5h-oSJ21EAet8H Video PlayList]
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== Overview ==
 +
 +
This CPU is intended to be used as an I/O Processor. The CPU can be used as a Microcontroller replacement in many applications. It implemented in an FPGA. It is useful for offloading polled I/O or replacing CPUs in small applications. The majority of these applications deal with 8-bit data and that's where this CPU excels.
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== Features Set ==
 +
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* 16-bit CPU
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** Simple/consistent opcode bit fields
 +
*** Instructions are always only 16-bits wide
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** 4-bit opcode
 +
*** Some sub-instructions allow more than 16 instructions
 +
** 4-bit register field (shared with address/offset)
 +
** 8-bit constant (shared with address/offset)
 +
* 12.5 MIPS (4 of 50 MHz FPGA clocks)
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* [[IOP16 Register File|Register File]]
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** 8 registers
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*** Reserved space in instruction set for up to 16 registers
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** Registers are 8-bits
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== IOP16 Block Diagram ==
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<img src="https://cdn.hackaday.io/images/4227861624281074683.PNG"></img>
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== Instruction Set ==
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* [[IOP16 Instructions Detail]]
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== Assembler ==
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* [[Assembler|Table driven Assembler]]
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** Input comes from a CSV file
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** Outputs .MIF and Listing files
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*** MIF (Memory Initialization File) is Altera ROM initialization File
 +
 +
== Hardware Requirements ==
 +
 +
* Targeted at an FPGA implementation
 +
** The CPU could easily be run on pretty much any FPGA
 +
** Coded in VHDL
 +
* Very small LUT/Memory footprint in FPGA
 +
** Uses 226 logic cells in an Altera EP4 FPGA
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** Requires a minimum 2 of 1K SRAM blocks (depends on program size)
 +
*** Trade-off - SRAM could be replaced with logic cells (in theory)
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=== Target Hardware ===
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* The initial targeted hardware is the [https://www.aliexpress.com/item/33007471265.html?spm=a2g0o.store_pc_groupList.8148356.5.2f5a77a2912sNP QMTECH EP4CE15 FPGA card]
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** This FPGA is inexpensive and powerful
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** The CPU takes up very little of the resources of the FPGA
 +
 +
<img src="https://raw.githubusercontent.com/douggilliland/Design_A_CPU/main/Docs/CycloneIV_Starter_Kit_P528-cropped.jpg?token=AALUDDTXH4AAMPMJKRVL2LDA5BCOI"></img>
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* https://github.com/ChinaQMTECH/CYCLONE_IV_STARTER_KIT QMTECH CYCLONE IV STARTER KIT GitHub]
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** [https://github.com/douggilliland/FPGA_Cards/tree/master/QMTECH_CYCLONE_IV_STARTER_KIT QMTECH FPGA Files Reflector]
 +
* [https://www.aliexpress.com/item/33007471265.html?spm=a2g0o.store_pc_groupList.8148356.5.2f5a77a2912sNP QMTECH EP4CE15 FPGA card] - AliExpress page
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== Peripheral Support ==
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* Extensive [[IOP16B Peripheral Support|Peripheral Support]]
 +
* 8-bit address (controls up to 256 peripherals)
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* 8-bit data
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* Read strobe (a couple of clocks wide)
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* Write strobe (a couple of clocks wide)
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== Code Examples ==
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* [https://github.com/douggilliland/Design_A_CPU/blob/main/CPU_Code/README.mediawiki IOP16 Code Examples]
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== External References ==
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* [https://hackaday.io/project/180452-small-cpu-in-vhdl Hackaday.io page].
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* [https://www.youtube.com/watch?v=ZtEJHF-pVU0&list=PLn__0BqzWEWNspQ0xkG5h-oSJ21EAet8H YouTube Video Series].
  
 
== Example Applications ==
 
== Example Applications ==

Revision as of 14:01, 10 April 2022

16-bit I/O Processor Design

Video PlayList

Overview

This CPU is intended to be used as an I/O Processor. The CPU can be used as a Microcontroller replacement in many applications. It implemented in an FPGA. It is useful for offloading polled I/O or replacing CPUs in small applications. The majority of these applications deal with 8-bit data and that's where this CPU excels.

Features Set

  • 16-bit CPU
    • Simple/consistent opcode bit fields
      • Instructions are always only 16-bits wide
    • 4-bit opcode
      • Some sub-instructions allow more than 16 instructions
    • 4-bit register field (shared with address/offset)
    • 8-bit constant (shared with address/offset)
  • 12.5 MIPS (4 of 50 MHz FPGA clocks)
  • Register File
    • 8 registers
      • Reserved space in instruction set for up to 16 registers
    • Registers are 8-bits

IOP16 Block Diagram

<img src="https://cdn.hackaday.io/images/4227861624281074683.PNG"></img>

Instruction Set

Assembler

  • Table driven Assembler
    • Input comes from a CSV file
    • Outputs .MIF and Listing files
      • MIF (Memory Initialization File) is Altera ROM initialization File

Hardware Requirements

  • Targeted at an FPGA implementation
    • The CPU could easily be run on pretty much any FPGA
    • Coded in VHDL
  • Very small LUT/Memory footprint in FPGA
    • Uses 226 logic cells in an Altera EP4 FPGA
    • Requires a minimum 2 of 1K SRAM blocks (depends on program size)
      • Trade-off - SRAM could be replaced with logic cells (in theory)

Target Hardware

  • The initial targeted hardware is the QMTECH EP4CE15 FPGA card
    • This FPGA is inexpensive and powerful
    • The CPU takes up very little of the resources of the FPGA

<img src="https://raw.githubusercontent.com/douggilliland/Design_A_CPU/main/Docs/CycloneIV_Starter_Kit_P528-cropped.jpg?token=AALUDDTXH4AAMPMJKRVL2LDA5BCOI"></img>

Peripheral Support

  • Extensive Peripheral Support
  • 8-bit address (controls up to 256 peripherals)
  • 8-bit data
  • Read strobe (a couple of clocks wide)
  • Write strobe (a couple of clocks wide)

Code Examples

External References

Example Applications

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