View source for IOP16 16-bit I/O CPU Design

= Overview =

This CPU is intended to be used as an [https://www.brainkart.com/article/I-O-Processors_8637/ I/O Processor]. The CPU can be used as a Microcontroller replacement in many applications. It can be embedded into an FPGA with a separate Host Computer off-loading tedious I/O programming. It is useful for offloading polled I/O or replacing CPUs in small applications. The majority of these applications deal with 8-bit data and that's where this CPU excels.

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[https://www.youtube.com/watch?v=ZtEJHF-pVU0&list=PLn__0BqzWEWNspQ0xkG5h-oSJ21EAet8H Video PlayList]

= Features Set =

* [https://github.com/douggilliland/IOP16/tree/main/IOP16_CPU 16-bit CPU]
* Simple/consistent [[IOP16 Opcodes|opcode bit fields]]
** Instructions are always 16-bits wide
** 4-bit opcode
*** Some "sub-instructions" allow more than 16 instructions
** 4-bit register field (shared with address/offset)
** 8-bit constant (shared with address/offset)
* High enough [[IOP-16 Performance]] - 12.5 MIPS
** 4 of 50 MHz FPGA clocks
* [[IOP16 Register File|Register File]]
** 4, 8, or 13 General Purpose registers
** 3 constant value registers
** Registers are 8-bits
* 12-bit of Program address (up to 4K instructions)
* [[Return Stack|IOP-16 Stack]]
** 0 (none)
** 1 deep
** Optionally deeper as build option (uses SRAM)

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= IOP16 Block Diagram =

[[file:IOP16_Block-Diagram.png]]

= Instruction Set =

* [[IOP16 Instructions Detail]]

= Assembler =

* [[IOP16 Assembler|Table driven Assembler]]
** Input comes from a CSV file
** Outputs .MIF and Listing files
*** MIF (Memory Initialization File) is Altera ROM initialization File

= Hardware Requirements =

* Targeted at an FPGA implementation
** The CPU could easily be run on pretty much any FPGA
** Coded in VHDL

== Resources ==

* Very small LUT/Memory footprint in FPGA
* Uses 271 logic cells in an Altera EP4 FPGA
* Uses 76 registers in an Altera EP4 FPGA
* Requires a minimum 1 of 1K SRAM blocks (depends on program size)
*** Trade-off - SRAM could be replaced with logic cells (in theory)

== Target Hardware ==

[[File:CycloneIV_Starter_Kit_P528-720px.jpg]]

* The initial targeted hardware is the [[QMTECH_EP4CE15_FPGA_Starter_Kit|QMTECH EP4CE15 FPGA Starter Kit card]]
** This FPGA is inexpensive and powerful
** The CPU takes up very little of the resources of the FPGA
* [https://github.com/ChinaQMTECH/CYCLONE_IV_STARTER_KIT QMTECH CYCLONE IV STARTER KIT GitHub]
* [https://github.com/douggilliland/FPGA_Cards/tree/master/QMTECH_CYCLONE_IV_STARTER_KIT QMTECH FPGA Files] Reflector
* [https://www.aliexpress.com/item/33007471265.html?spm=a2g0o.store_pc_groupList.8148356.5.2f5a77a2912sNP QMTECH EP4CE15 FPGA card] - AliExpress page

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=== Build on Cyclone 10 FPGA ===

* [https://github.com/douggilliland/IOP16/tree/main/Higher_Level_Examples/TestIOP16_Max_Cy10 Cyclone 10 FPGA example]

=== Build into MultiComp in a Box ===

* [[Multicomp in a Box]]

= Peripheral Support =

* [[IOP16 Peripheral Support|Extensive Peripheral Support]]
* 8-bit address (controls up to 256 peripherals)
* 8-bit data
* Read strobe (a couple of clocks wide)
* Write strobe (a couple of clocks wide)

= Code Examples =

Here are some Code and FPGA build example applications

* [https://github.com/douggilliland/Design_A_CPU Design a CPU Base Code] - GitHub

== Blink LED ==

Almost minimal design = CPU + Timer + LED

* [https://github.com/douggilliland/IOP16/tree/main/Higher_Level_Examples/TestIOP16B TestIOP16B]
* [https://github.com/douggilliland/IOP16/blob/main/IOP16_Code/testTimer/testTimer.csv testTimer Code]

== ANSI Terminal ==

* [https://github.com/douggilliland/IOP16/tree/main/Higher_Level_Examples/ANSITerm2 ANSITerm2 FPGA]
* [https://github.com/douggilliland/Design_A_CPU/tree/main/CPU_Code/Application_Code/ANSITerm03 ANSITerm03 Code]
* [https://hackaday.io/project/180415-ansi-terminal-in-an-fpga Hackaday ANSI Terminal in an FPGA]

== 6800 Microprocessor Front Panel ==

* [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15/M6800_MIKBUG_FrontPanel01 6800 CPU with Front Panel]
* [[Front Panel for 8 Bit Computers V2]]

=== Front Panel Loopback ===

* [https://github.com/douggilliland/IOP16/tree/main/Higher_Level_Examples/Front%20Panel%20Examples/FrontPanel01_Test_LoopBack Front Panel Loopback FPGA]
* [https://github.com/douggilliland/Design_A_CPU/tree/main/CPU_Code/Application_Code/FP01_LOOP4 Front Panel Loopback Code]
* [https://hackaday.io/project/180199-8-bit-computer-front-panel Hackaday Front Panel]

= IOP16 Extending/Embedding Guide =

* [[Extend IOP16 minimal example|Extend IOP16 minimal example by adding peripherals]]
* [[Embed IOP16|Embed IOP16 into another design]]

= External References =

* [https://hackaday.io/project/180452-small-cpu-in-vhdl Hackaday.io page].
* [https://www.youtube.com/watch?v=ZtEJHF-pVU0&list=PLn__0BqzWEWNspQ0xkG5h-oSJ21EAet8H YouTube Video Series].