IOP16 UART

UART and Baud Rate Generator

UART Programming Interface

• Interface mimics ACIA software interface address/control/status contents
  • ACIA datasheet
• Two addresses, Control/status and data access

Status Register (Read)

• Register Select = 0
• Bits

d0 = RDRF = Receive Data Register Full (1 = data is ready to read)
d1 = TDRE = Transmit Data Register Empty (1 = transmit is ready to send out data)
d2 = DCD  = Data Carrier Detect (0 = carrier present - hardwired)
d3 = CTS  = Clear to Send (0 = Clear to Send - ready to accept data - hardwired)
d7 = IRQ  = Interrupt Request (1 = Interrupt present)

Control Register (Write)

• Register Select = 0
• Bits

d1,d0 = Control (11 = Master Reset)
d6,d5 = TC = Transmitter Control (RTS = Transmitter Interrupt Enable/Disable)
d7    = Interrupt Enable (1=enable interrupts)

Data Register (Read/Write)

• Register Select = 1
  • Read = Read data from the data register (not implemented due to kbd removal)
  • Write = Write data to the data register

Baud Rate Generator for buffered UART

• Assumes 50 MHz clock
• Pass Baud Rate in BAUD_RATE generic as integer value (300, 9600, 115,200)
  • Legal values are 115200, 38400, 19200, 9600, 4800, 2400, 1200, 600, 300
• Call with

BaudRateGen : entity work.BaudRate6850
GENERIC map (
	BAUD_RATE	=>  115200
)
PORT map (
	i_CLOCK_50	=> i_CLOCK_50,
	o_serialEn	=> serialEn
);

VHDL Entities

UART Entity

-- ____________________________________________________________________________________
-- ACIA UART serial interface
-- Grant Searle's UART driver from Multicomp
-- Modified by Neal Crook from Grant Searle's code to use rising clk
--   and to use baud rate enables rather than clocks
-- https://github.com/nealcrook/multicomp6809
w_UARTWr <= '1' when ((w_peripAddr(7 downto 1) = "0000010") and (w_peripWr = '1')) else '0';
W_UARTRd <= '1' when ((w_peripAddr(7 downto 1) = "0000010") and (w_peripRd = '1')) else '0';

acia: entity work.bufferedUART
  port map (
    clk     => i_clock,     
    n_WR    => not w_UARTWr,
    n_rd    => not W_UARTRd,
    regSel  => w_peripAddr(0),
    dataIn  => w_peripDataFromCPU,
    dataOut => w_UARTDataOut,
    rxClkEn => w_serialEn,
    txClkEn => w_serialEn,
    rxd     => i_uart_rx,
    txd    => o_uart_tx
);

Baud Rate Generator Entity

-- ____________________________________________________________________________________
-- Baud Rate Generator as an entity with passed baud rate
-- Legal BAUD_RATE values are 115200, 38400, 19200, 9600, 4800, 2400, 1200, 600, 300
BaudRateGen : entity work.BaudRate6850
  GENERIC map (
    BAUD_RATE	=>  115200
  )
  PORT map (
    i_CLOCK_50	=> i_clock,
    o_serialEn	=> w_serialEn
);