IOP16 ANSI Display

Multicomp FPGA (VHDL Template) VGA

Interface mimics ACIA software interface address/control/status contents

• ACIA datasheet

Programming Interface

• Two addresses, Control/status and data access

Status Register

• Register Select = 0
• Read/Write = Read
  • d0 = RDRF = Receive Data Register Full (1 = data is ready to read)
  • d1 = TDRE = Transmit Data Register Empty (1 = transmit is ready to send out data)
  • d2 = DCD = Data Carrier Detect (0 = carrier present - hardwired)
  • d3 = CTS = Clear to Send (0 = Clear to Send - ready to accept data - hardwired)
  • d7 = IRQ = Interrupt Request (1 = Interrupt present)

Control Register

• Register Select = 0
• Read/Write = Write
  • d1,d0 = Control (11 = Master Reset)
  • d6,d5 = TC = Transmitter Control (RTS = Transmitter Interrupt Enable/Disable)
  • d7 = Interrupt Enable (1=enable interrupts)

Data Register

• Register Select = 1
  • Read = Read data from the data register (not implemented due to kbd removal)
  • Write = Write data to the data register

ANSI ESC Codes

<img src="http://land-boards.com/blwiki/images/4/44/ANSI_001.PNG"></img> <img src="http://land-boards.com/blwiki/images/7/7d/ANSI_002.PNG"></img>

Entity

-- ____________________________________________________________________________________
-- Grant Searle's VGA driver from Multicomp
-- DGG removed the PS/2 keyboard, Composite output and CTS
-- Interface matches ACIA software interface address/control/status contents
o_vga_r <= w_videoR(1)&w_videoR(1)&w_videoR(0)&w_videoR(0)&w_videoR(0);					-- Map VGA pins 2:2:2 to 5:6:5
o_vga_g <= w_videoG(1)&w_videoG(1)&w_videoG(0)&w_videoG(0)&w_videoG(0)&w_videoG(0);
o_vga_b <= w_videoB(1)&w_videoB(1)&w_videoB(0)&w_videoB(0)&w_videoB(0);

W_VDUWr <= '1' when ((w_peripAddr(7 downto 1) = "0000011") and (w_peripWr = '1')) else '0';
W_VDURd <= '1' when ((w_peripAddr(7 downto 1) = "0000011") and (w_peripRd = '1')) else '0';
vdu : entity work.ANSIDisplayVGA
  GENERIC map (
    EXTENDED_CHARSET    => 0, -- 1 = 256 chars
                              -- 0 = 128 chars
    COLOUR_ATTS_ENABLED => 0, -- 1 = Color for each character
                              -- 0 = Color applied to whole display
    SANS_SERIF_FONT     => 1  -- 0 => use conventional CGA font
                              -- 1 => use san serif font
)
  port map (
    clk     => i_clock,
    n_reset => w_resetClean_n,
    -- CPU interface
    n_WR    => not W_VDUWr,
    n_rd    => not W_VDURd,
    regSel  => w_peripAddr(0),
    dataIn  => w_peripDataFromCPU,
    dataOut => w_VDUDataOut,
    -- VGA video signals
    hSync   => o_vga_hs,
    vSync   => o_vga_vs,
    videoR0 => w_videoR(0),
    videoR1 => w_videoR(1),
    videoG0 => w_videoG(0),
    videoG1 => w_videoG(1),
    videoB0 => w_videoB(0),
    videoB1 => w_videoB(1)
);

• Resource usage can be reduced by changing the generics below
  • EXTENDED_CHARSET=0, COLOUR_ATTS_ENABLED=0 - Uses 3 M9K blocks
  • EXTENDED_CHARSET=1, COLOUR_ATTS_ENABLED=0 - Uses 4 M9K blocks
  • EXTENDED_CHARSET=0, COLOUR_ATTS_ENABLED=1 - Uses 5 M9K blocks
  • EXTENDED_CHARSET=1, COLOUR_ATTS_ENABLED=1 - Uses 6 M9K blocks

Resources (EP4CE15)

• Logic Cells: 969
• Registers: 203
• Memory Bits: 24576