Difference between revisions of "Embed IOP16"

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(Created page with "== Example Applications == * [https://hackaday.io/project/180415-ansi-terminal-in-an-fpga Hackaday ANSI Terminal in an FPGA] * [https://github.com/douggilliland/Design_A_CPU...")
 
 
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= Overview =
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* This is a guide to embedding the IOP16 into another design
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* This is not the same as [[Extend_IOP16_minimal_example|Extending IOP16 minimal example]]
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* This guide requires general familiarity with [[IOP16_16-bit_I/O_CPU_Design|IOP16 16-bit I/O CPU Design]]
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= Examples of Embedded IOP16 =
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* Working examples
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** [https://github.com/douggilliland/Retro-Computers/tree/master/PDP-8/PDP8_OpenCores/RETRO-EP4CE15_CYCLONE_IV_VDU PDP-8 with ANSI Terminal example]
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** [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15/M6800_MIKBUG_FrontPanel01 M6800 CPU with Front Panel Example]
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== PDP-8 with ANSI Terminal Example ==
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* Embeds [https://github.com/douggilliland/Retro-Computers/tree/master/PDP-8/PDP8_OpenCores/RETRO-EP4CE15_CYCLONE_IV_VDU/ANSITerm ANSITerm] to [https://github.com/douggilliland/Retro-Computers/tree/master/PDP-8/PDP8_OpenCores/RETRO-EP4CE15_CYCLONE_IV_VDU PDP-8]
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** Reads keyboard and writes to UART (connected at the higher level to PDP-8)
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** Reads UART (connected at the higher level to PDP-8) and writes to the screen
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* Connections through Serial Tx/Rx lines to existing design
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== 8-bit CPU with Front Panel Example ==
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* [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15/M6800_MIKBUG_FrontPanel01 M6800 Front Panel Build]
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** M6800 CPU
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** 32KB internal SRAM
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** MIKBUG ROM
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** Uses [[Front_Panel_For_8_Bit_Computers|Front Panel For 8 Bit Computers]] to read/write Dual Ported CPU memory
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** Performs low-level I2C communications with Front Panel
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* Controle CPU Run/Halt state
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= CPU Entity =
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* The CPU entity has the minimal connection needed to use the CPU in an embedded application
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* Copy/paste the CPU entity into the next higher-level VDHL file
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<pre>
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--  IOP16 Peripheral bus
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signal w_periphAdr        : std_logic_vector(7 downto 0);
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signal w_peripDataToCPU  : std_logic_vector(7 downto 0);
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signal w_peripDataFromCPU : std_logic_vector(7 downto 0);
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signal w_periphWr        : std_logic;
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signal w_periphRd        : std_logic;
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 +
CPU : ENTITY work.cpu_001
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  generic map (
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    INST_ROM_SIZE_PASS => 512, -- Instruction ROM size
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    STACK_DEPTH_PASS  => 4    -- JSR/RTS nesting depth - Stack size 2^n - n (4-12 locations)
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  )
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PORT map
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(
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  i_clock            => i_clock,            -- 50 MHz clock
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  i_resetN          => w_resetClean_n,    -- Reset CPU active low
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  i_peripDataToCPU  => w_peripDataToCPU,  -- Data from the Peripherals to the CPU
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  -- Peripheral bus
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  o_peripAddr        => w_peripAddr,        -- Peripheral address bus (256 I/O locations)
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  o_peripDataFromCPU => w_peripDataFromCPU, -- Data from CPU to Peripherals
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  o_peripWr          => w_peripWr,          -- Write strobe
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  o_peripRd          => w_peripRd          -- Read strobe
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);
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</pre>
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== CPU Entity ==
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* Two generics can be modified
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** INST_ROM_SIZE_PASS - Instruction ROM size
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*** Legal sizes are 512W, 1KW, 2KW, 4KW
 +
**** 512W uses 1 of 1K Blocks in EP4CE15 FPGA
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*** Should match ROM application size
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** STACK_DEPTH_PASS - JSR/RTS nesting depth - Stack size 2^n - n (4-12 locations)
 +
*** Legal sizes
 +
**** 0 - None
 +
**** 1 - Single deep - Doesn't need SRAM
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**** 2, 3, 4 - Needs SRAM
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== IOP16 CPU Resources ==
 +
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* Logic Cells: 271
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* Registers: 76
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* Memory bits: 8192 (512W)
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== Example Applications ==
 
== Example Applications ==
  
 
* [https://hackaday.io/project/180415-ansi-terminal-in-an-fpga Hackaday ANSI Terminal in an FPGA]
 
* [https://hackaday.io/project/180415-ansi-terminal-in-an-fpga Hackaday ANSI Terminal in an FPGA]
 
* [https://github.com/douggilliland/Design_A_CPU Design a CPU] - GitHub
 
* [https://github.com/douggilliland/Design_A_CPU Design a CPU] - GitHub
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== Connect to High Level ==
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* Peripheral elements are linked to the Peripheral address, data busses and strobes

Latest revision as of 17:21, 11 April 2022

Overview

Examples of Embedded IOP16

PDP-8 with ANSI Terminal Example

  • Embeds ANSITerm to PDP-8
    • Reads keyboard and writes to UART (connected at the higher level to PDP-8)
    • Reads UART (connected at the higher level to PDP-8) and writes to the screen
  • Connections through Serial Tx/Rx lines to existing design

8-bit CPU with Front Panel Example

CPU Entity

  • The CPU entity has the minimal connection needed to use the CPU in an embedded application
  • Copy/paste the CPU entity into the next higher-level VDHL file
--  IOP16 Peripheral bus
signal w_periphAdr        : std_logic_vector(7 downto 0);
signal w_peripDataToCPU   : std_logic_vector(7 downto 0);
signal w_peripDataFromCPU : std_logic_vector(7 downto 0);
signal w_periphWr         : std_logic;
signal w_periphRd         : std_logic;

CPU : ENTITY work.cpu_001
  generic map ( 
    INST_ROM_SIZE_PASS => 512, -- Instruction ROM size
    STACK_DEPTH_PASS   => 4    -- JSR/RTS nesting depth - Stack size 2^n - n (4-12 locations)
  )
PORT map 
(
  i_clock            => i_clock,            -- 50 MHz clock
  i_resetN           => w_resetClean_n,     -- Reset CPU active low
  i_peripDataToCPU   => w_peripDataToCPU,   -- Data from the Peripherals to the CPU
  -- Peripheral bus
  o_peripAddr        => w_peripAddr,        -- Peripheral address bus (256 I/O locations)
  o_peripDataFromCPU => w_peripDataFromCPU, -- Data from CPU to Peripherals
  o_peripWr          => w_peripWr,          -- Write strobe
  o_peripRd          => w_peripRd           -- Read strobe
);

CPU Entity

  • Two generics can be modified
    • INST_ROM_SIZE_PASS - Instruction ROM size
      • Legal sizes are 512W, 1KW, 2KW, 4KW
        • 512W uses 1 of 1K Blocks in EP4CE15 FPGA
      • Should match ROM application size
    • STACK_DEPTH_PASS - JSR/RTS nesting depth - Stack size 2^n - n (4-12 locations)
      • Legal sizes
        • 0 - None
        • 1 - Single deep - Doesn't need SRAM
        • 2, 3, 4 - Needs SRAM

IOP16 CPU Resources

  • Logic Cells: 271
  • Registers: 76
  • Memory bits: 8192 (512W)

Example Applications

Connect to High Level

  • Peripheral elements are linked to the Peripheral address, data busses and strobes
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