IOP16 UART

UART and Baud Rate Generator

UART Programming Interface

• Interface mimics ACIA software interface address/control/status contents
  • ACIA datasheet
• Two addresses, Control/status and data access

Status Register (Read)

• Register Select = 0
• Bits

d0 = RDRF = Receive Data Register Full (1 = data is ready to read)
d1 = TDRE = Transmit Data Register Empty (1 = transmit is ready to send out data)
d2 = DCD  = Data Carrier Detect (0 = carrier present - hardwired)
d3 = CTS  = Clear to Send (0 = Clear to Send - ready to accept data - hardwired)
d7 = IRQ  = Interrupt Request (1 = Interrupt present)

Control Register (Write)

• Register Select = 0
• Bits

d1,d0 = Control (11 = Master Reset)
d6,d5 = TC = Transmitter Control (RTS = Transmitter Interrupt Enable/Disable)
d7    = Interrupt Enable (1=enable interrupts)

Data Register (Read/Write)

• Register Select = 1
  • Read = Read data from the data register (not implemented due to kbd removal)
  • Write = Write data to the data register

Baud Rate Generator for buffered UART

• Assumes 50 MHz clock
• Pass Baud Rate in BAUD_RATE generic as integer value (300, 9600, 115,200)
  • Legal values are 115200, 38400, 19200, 9600, 4800, 2400, 1200, 600, 300
• Call with

BaudRateGen : entity work.BaudRate6850
GENERIC map (
	BAUD_RATE	=>  115200
)
PORT map (
	i_CLOCK_50	=> i_CLOCK_50,
	o_serialEn	=> serialEn
);

UART and Baud Rate Generator VHDL Entities

• Code to add UART to the IOP16 top file

Pins

• Add to top level entity

-- UART
rxd1      : in std_logic := '1';  -- Hardware Handshake needed
txd1      : out std_logic;
cts1      : in std_logic := '1';
rts1      : out std_logic;
serSelect : in std_logic := '1';  -- Jumper with pullup in FPGA for selecting serial between ACIA (installed) and VDU (removed)

Signals

• Add signals to architecture section

-- Decodes/Strobes
...
  signal w_wrUart				:	std_logic;
  signal w_rdUart				:	std_logic;

-- Interfaces
..
  signal w_UartDataOut			:	std_logic_vector(7 downto 0);

-- Serial clock enable
  signal W_serialEn      		: std_logic;		-- 16x baud rate clock	

UART Entity

-- 6850 style UART
UART: entity work.bufferedUART
  port map (
    clk     			=> i_CLOCK_50,
    -- Strobes
    n_wr				=> not w_wrUart,
    n_rd    			=> not w_rdUart,
    -- CPU 
    regSel  			=> w_periphAdr(0),
    dataIn  			=> w_periphOut,
    dataOut 			=> w_UartDataOut,
    -- Clock strobes
    rxClkEn 			=> serialEn,
    txClkEn 			=> serialEn,
   -- Serial I/F
    rxd     			=> rxd1,
    txd     			=> txd1,
    n_rts   			=> rts1,
    n_cts   			=> cts1
  );

Baud Rate Generator Entity

-- ____________________________________________________________________________________
-- Baud Rate Generator as an entity with passed baud rate
-- Legal BAUD_RATE values are 115200, 38400, 19200, 9600, 4800, 2400, 1200, 600, 300
BaudRateGen : entity work.BaudRate6850
  GENERIC map (
    BAUD_RATE	=>  115200
  )
  PORT map (
    i_CLOCK_50	=> i_clk,
    o_serialEn	=> w_serialEn
);

FPGA Resources (EP4CE15)

• UART
  • Logic Cells: 183
  • Registers: 94
  • Memory Bits: 128
  • M9Ks: 1
• Baud Rate Generator
  • Logic Cells: 14
  • Registers: 13
  • Memory Bits: 0
  • M9Ks: 0