RETRO-65C816

Features

• Design based on RETRO-EP4CE15 card
  • Adds 65C816 CPU
  • 5V level translator for keyboard
  • 5V header moved to board edge
• 65C816 CPU
  • 3.3V
  • 8 MHz
  • All pins are brought to FPGA
  • Address A0-A15 and Data lines also go directly to the SRAM
  • FPGA can have the ROM internally or download it to the SRAM
• 1MB SRAM
  • 45nS access time
• USB B
  • FTDI USB to TTL
  • Tx/Rx LEDs
• VGA
  • 2:2:2 R:G:B
• PS/2 keyboard
  • 5V KEYBOARD
  • Level translator to 3.3V for FPGA
• SD card socket
  • Full-sized SD
• QMTECH FPGA card mounts on top
  • QMTECH EP4CE15 FPGA Card
  • QMTECH EP4CE55 FPGA Card
  • QMTECH 5CEFA2F23 FPGA Card
  • QMTECH Cyclone 10CL006 FPGA Card
• 95x95mm card
  • ODAS form factor
• (4) 6-32 Mounting holes

65C816 CPU

65C816 Datasheet

Block Diagram

Timing

Connectors

H1 - 5V

• Install jumper to power card from USB

H2 - VREG I/O Conn

• Power to J1

J1 - I/O Connector

• 50-pin I/O Connector

J2 - Keyboard

• 1x4 header

J4 - USB B Serial/Power

• Serial to/from FTDI
• Can power the card

J5 - 5V/GND

• 5V/ground for external 5V logic

J7

U7 PIN	EP4CE15	EP4CE55	5CEFA2	CYC 10	FUNCTION
1	GND	GND	GND	GND	GND
2	GND	GND	GND	GND	GND
3	3.3V	3.3V	3.3V	3.3V	3.3V
4	3.3V	3.3V	3.3V	3.3V	3.3V
5	GND	GND	GND	GND	GND
6	GND	GND	GND	GND	GND
7	PIN_R1	PIN_R1	PIN_AA2	PIN_G1	PS2CLK
8	PIN_R2	PIN_R2	PIN_AA1	PIN_G2	PS2DAT
9	PIN_P1	PIN_P1	PIN_Y3	PIN_D1	SRAMA4
10	PIN_P2	PIN_P2	PIN_W2	PIN_C2	SRAMA5
11	PIN_N1	PIN_N1	PIN_U1	PIN_B1	SRAMA3
12	PIN_N2	PIN_N2	PIN_U2	PIN_F5	SRAMA6
13	PIN_M1	PIN_M1	PIN_N1	PIN_D3	SRAMA2
14	PIN_M2	PIN_M2	PIN_N2	PIN_C3	SRAMA7
15	PIN_J1	PIN_J1	PIN_L1	PIN_B3	SRAMA1
16	PIN_J2	PIN_J2	PIN_L2	PIN_A3	SRAM0E_N
17	PIN_H1	PIN_H1	PIN_G1	PIN_B4	SRAMA0
18	PIN_H2	PIN_H2	PIN_G2	PIN_A4	SRAMA8
19	PIN_F1	PIN_F1	PIN_E2	PIN_E5	SRAMCS_N
20	PIN_F2	PIN_F2	PIN_D3	PIN_A2	SRAMD7
21	PIN_E1	PIN_E1	PIN_C1	PIN_D4	SRAMD0
22	PIN_D2	PIN_D2	PIN_C2	PIN_E6	SRAMD6
23	PIN_C1	PIN_C1	PIN_G6	PIN_C6	SRAMD1
24	PIN_C2	PIN_C2	PIN_H6	PIN_D6	SRAMD5
25	PIN_B1	PIN_B1	PIN_G8	PIN_B5	SRAMD2
26	PIN_M11	PIN_M11	PIN_H8	PIN_A5	SRAMD4
27	PIN_R14	PIN_R14	PIN_F7	PIN_B6	SRAMD3
28	PIN_N13	PIN_N13	PIN_E7	PIN_A6	SRAMA9
29	PIN_N14	PIN_N14	PIN_D6	PIN_B7	SRAMWE_N
30	PIN_P14	PIN_P14	PIN_C6	PIN_A7	SRAMA10
31	PIN_P16	PIN_P16	PIN_E9	PIN_D8	SRAMA19
32	PIN_R16	PIN_R16	PIN_D9	PIN_C8	SRAMA11
33	PIN_N16	PIN_N16	PIN_B5	PIN_D9	SRAMA18
34	PIN_N15	PIN_N15	PIN_A5	PIN_C9	SRAMA12
35	PIN_M16	PIN_M16	PIN_B6	PIN_B8	SRAMA17
36	PIN_M15	PIN_M15	PIN_B7	PIN_A8	SRAMA13
37	PIN_L16	PIN_L16	PIN_A7	PIN_B9	SRAMA16
38	PIN_L15	PIN_L15	PIN_A8	PIN_A9	SRAMA14
39	PIN_P15	PIN_P15	PIN_A9	PIN_E9	N/C
40	PIN_M12	PIN_M12	PIN_A10	PIN_E8	SRAMA15
41	PIN_L14	PIN_L14	PIN_B10	PIN_E11	N/C
42	PIN_L13	PIN_L13	PIN_C9	PIN_E10	N/C
43	PIN_K16	PIN_K16	PIN_G10	PIN_A10	USBRX/FPGATX
44	PIN_K15	PIN_K15	PIN_F10	PIN_B10	USBCTS/FPGARTS
45	PIN_K12	PIN_K12	PIN_C11	PIN_D12	USBTX/FPGARX
46	PIN_J12	PIN_J12	PIN_B11	PIN_D11	UBSRTS/FPGACTS
47	PIN_J14	PIN_J14	PIN_B12	PIN_B11	CD_DET
48	PIN_J13	PIN_J13	PIN_A12	PIN_A11	N/C
49	PIN_K11	PIN_K11	PIN_E12	PIN_B12	REDLO
50	PIN_J11	PIN_J11	PIN_D12	PIN_A12	REDHI
51	PIN_G11	PIN_G11	PIN_D13	PIN_B13	GRNLO
52	PIN_F11	PIN_F11	PIN_C13	PIN_A13	GRNHI
53	PIN_F13	PIN_F13	PIN_B13	PIN_B14	BLULO
54	PIN_F14	PIN_F14	PIN_A13	PIN_A14	BLUHI
55	PIN_F10	PIN_F10	PIN_A15	PIN_D14	HSYNC
56	PIN_F9	PIN_F9	PIN_A14	PIN_C14	VSYNC
57	PIN_E16	PIN_E16	PIN_B15	PIN_B16	SDCS_N
58	PIN_E15	PIN_E15	PIN_C15	PIN_A15	SD_MOSI
59	PIN_D16	PIN_D16	PIN_C16	PIN_C16	SD_SCK
60	PIN_D15	PIN_D15	PIN_B16	PIN_C15	SD_MISO
61	GND	GND	GND	GND	GND
62	GND	GND	GND	GND	GND
63	VIN	VIN	VIN	VIN	VIN
64	VIN	VIN	VIN	VIN	VIN

P1 - VGA

• DB-15HD connector
• 2:2:2 R:G:B

P2 - PS/2 Keyboard

• Purple DIN-6 for PS/2 keyboard

P4 - SD Card

Mechanicals

MultiComp On RETRO-65C816 VHDL Code

• MultiComp On RETRO-65C816 GitHub page

References/Notes

• On the usefulness of 65816 as a 65C02 alternative
  • Helpful timing information

...potential for data bus contention during Ø2 low. My solution was two-fold: use VDA and VPA to qualify chip selects, and qualify read-accesses with Ø2. The former assures that an addressed device will not respond to selection until the address bus is truly valid—invalid bus states may occur during the execution of some instructions. The latter assures that a selected device will not drive the data bus when the '816 is presenting A16-A23 on it. This solution doesn't totally eliminate the risk of contention but greatly narrows the window of opportunity for it. The need for more stringent qualifying of D0-D7 would depend on the peripheral silicon on the bus. In the case of POC and the Ø2 rate I'm using (12.5 MHz maximum), everything gets off the data bus before the '816 starts to drive it with the bank address. That would not be the case if I were to increase Ø2 to 20 MHz, however.

Floating the buses with BE creates the odd situation where no valid address exists on A0-A15, which I daresay could cause a device to be selected solely because of a residual charge in bus capacitance. Also, BE floats the RWB signal*, which may trip up other logic that is dependent on RWB always being driven to one state or the other. The most fool-proof solution is the use of a data bus transceiver as you suggested, which is a straightforward method (74AC245 or 74AHC245 recommended if Ø2 will exceed 8 MHz).

Assembly Sheet

• RETRO-65C816 Rev 1 Assembly Sheet