Difference between revisions of "R32V2020 ALU Arithmetic operations"
Jump to navigation
Jump to search
Blwikiadmin (talk | contribs) (Created page with "* Add * Multiply ([https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-iv/cyiv-51004.pdf 18-bits native in FPGA]) * Subtract == Effects on the...") |
Blwikiadmin (talk | contribs) |
||
| Line 5: | Line 5: | ||
== Effects on the Condition Code Register (CCR) == | == Effects on the Condition Code Register (CCR) == | ||
| − | * Arithmetic operations affect the [[Register-File#r3__Condition_Code_Register| | + | * Arithmetic operations affect the [[R32V2020 Register-File#r3__Condition_Code_Register| |
Condition Code Register]] | Condition Code Register]] | ||
** Arithmetic operations set or clear the appropriate bits depending on the result of the operation | ** Arithmetic operations set or clear the appropriate bits depending on the result of the operation | ||
Revision as of 12:05, 10 April 2022
- Add
- Multiply (18-bits native in FPGA)
- Subtract
Effects on the Condition Code Register (CCR)
- Arithmetic operations affect the
Condition Code Register
- Arithmetic operations set or clear the appropriate bits depending on the result of the operation
