Difference between revisions of "QM Tech Cyclone V FPGA Board"
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[[File:CycloneV_SDRAM.png]] | [[File:CycloneV_SDRAM.png]] | ||
+ | |||
+ | # SDRAM | ||
+ | * sdRamClk | ||
+ | * sdRamClkEn | ||
+ | * n_sdRamCas | ||
+ | * n_sdRamCe | ||
+ | * n_sdRamRas | ||
+ | * n_sdRamWe | ||
+ | * sdRamAddr[0] | ||
+ | * sdRamAddr[1] | ||
+ | * sdRamAddr[2] | ||
+ | * sdRamAddr[3] | ||
+ | * sdRamAddr[4] | ||
+ | * sdRamAddr[5] | ||
+ | * sdRamAddr[6] | ||
+ | * sdRamAddr[7] | ||
+ | * sdRamAddr[8] | ||
+ | * sdRamAddr[9] | ||
+ | * sdRamAddr[10] | ||
+ | * sdRamAddr[11] | ||
+ | * sdRamAddr[12] | ||
+ | * sdRamAddr[13] | ||
+ | * sdRamAddr[14] | ||
+ | * sdRamData[0] | ||
+ | * sdRamData[1] | ||
+ | * sdRamData[2] | ||
+ | * sdRamData[3] | ||
+ | * sdRamData[4] | ||
+ | * sdRamData[5] | ||
+ | * sdRamData[6] | ||
+ | * sdRamData[7] | ||
+ | * sdRamData[8] | ||
+ | * sdRamData[9] | ||
+ | * sdRamData[10] | ||
+ | * sdRamData[11] | ||
+ | * sdRamData[12] | ||
+ | * sdRamData[13] | ||
+ | * sdRamData[14] | ||
+ | * sdRamData[15] | ||
== Resources == | == Resources == | ||
* [https://github.com/ChinaQMTECH/QM_CYCLONE_V GitHub Repo] | * [https://github.com/ChinaQMTECH/QM_CYCLONE_V GitHub Repo] |
Revision as of 13:38, 9 August 2020
- QMTECH Altera Intel FPGA Core Board Cyclone V CycloneV 5CEFA2F23 SDRAM
- On-Board FPGA: 5CEFA2F23I7N
- On-Board FPGA external crystal frequency: 50MHz
- 5CEFA2F23 has rich RAM resource up to 1,760Kb
- 5CEFA2F23 has 25K logic cells
- On-Board Micron MT25QL128A SPI Flash, 16M bytes for user configuration code
- On-Board Winbond 32MB SDRAM, W9825G6KH-6
- On-Board 3.3V power supply for FPGA by using MP2315 wide input range DC/DC
- 5CEFA2F23 core board has two 64p, 2.54mm pitch headers for extending 108 user IOs. All 108 user IOs are precisely designed with length matching
- 5CEFA2F23 core board has 3 user switches
- 5CEFA2F23 core board has 2 user LEDs
- 5CEFA2F23 core board has JTAG interface, by using 10p, 2.54mm pitch header
- 5CEFA2F23 core board PCB size is: 6.7cm x 8.4cm
- Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm
FPGA
SDRAM
- SDRAM
- sdRamClk
- sdRamClkEn
- n_sdRamCas
- n_sdRamCe
- n_sdRamRas
- n_sdRamWe
- sdRamAddr[0]
- sdRamAddr[1]
- sdRamAddr[2]
- sdRamAddr[3]
- sdRamAddr[4]
- sdRamAddr[5]
- sdRamAddr[6]
- sdRamAddr[7]
- sdRamAddr[8]
- sdRamAddr[9]
- sdRamAddr[10]
- sdRamAddr[11]
- sdRamAddr[12]
- sdRamAddr[13]
- sdRamAddr[14]
- sdRamData[0]
- sdRamData[1]
- sdRamData[2]
- sdRamData[3]
- sdRamData[4]
- sdRamData[5]
- sdRamData[6]
- sdRamData[7]
- sdRamData[8]
- sdRamData[9]
- sdRamData[10]
- sdRamData[11]
- sdRamData[12]
- sdRamData[13]
- sdRamData[14]
- sdRamData[15]