IOP16 ANSI Display

Multicomp FPGA (VHDL Template) VGA

Interface mimics ACIA software interface address/control/status contents

• ACIA datasheet

Programming Interface

• Two addresses, Control/status and data access

Status Register

• Register Select = 0
• Read/Write = Read
  • d0 = RDRF = Receive Data Register Full (1 = data is ready to read)
  • d1 = TDRE = Transmit Data Register Empty (1 = transmit is ready to send out data)
  • d2 = DCD = Data Carrier Detect (0 = carrier present - hardwired)
  • d3 = CTS = Clear to Send (0 = Clear to Send - ready to accept data - hardwired)
  • d7 = IRQ = Interrupt Request (1 = Interrupt present)

Control Register

• Register Select = 0
• Read/Write = Write
  • d1,d0 = Control (11 = Master Reset)
  • d6,d5 = TC = Transmitter Control (RTS = Transmitter Interrupt Enable/Disable)
  • d7 = Interrupt Enable (1=enable interrupts)

Data Register

• Register Select = 1
  • Read = Read data from the data register (not implemented due to kbd removal)
  • Write = Write data to the data register

ANSI ESC Codes

<img src="http://land-boards.com/blwiki/images/4/44/ANSI_001.PNG"></img> <img src="http://land-boards.com/blwiki/images/7/7d/ANSI_002.PNG"></img>

Acknowledgments

These files are from Neal Crook's port of the VHDL code to support VGA files (as snagged 2019-04-08) for Grant Searle's Multicomp Retro-Computer. Neal describes the enhancements here.

Grant's projects re-create late 1970's and early 1980's era vintage computers using inexpensive FPGA cards. The various parts that make up retro-computers are in each of the folders.

Our RetroComputing Wiki page is here.

Ownership

• Some of these files such as FPGA designs and software libraries were created by others.
  • There may be newer versions of these libraries "out there".
  • Some libraries even have the same names but don't work the same.
• Many of these files were created by me based on the work of others.

Warning

• Use at your own risk.
  • If you brick your part or it melt to a puddle, it's on you not me.