Timer Unit
- Operates as a One-shot counter with single value
- Count uS, mSec or secs (allows for different resolutions)
- Write to count value starts timer
- Poll timer status
Address Value Read/Write Data
0 uSec Count Write 0-255 uS count - write starts timer
1 mSec Count Write 0-255 mS count - write starts timer
2 Sec Count Write 0-255 sec count - write starts timer
3 Not Used Write Not used
0-3 Status Read 1 = Count In progresss
0 = Done
Entity
-- ____________________________________________________________________________________
-- Timer Unit
w_timerAdr <= '1' when (w_peripAddr(7 downto 2) = "000010") else '0';
timerUnit : entity work.TimerUnit
port map
(
-- Clock and Reset
i_clk => i_clock,
i_n_reset => w_resetClean_n,
-- The key and LED on the FPGA card
i_timerSel => w_timerAdr,
i_writeStrobe => w_peripWr,
i_regSel => w_peripAddr(1 downto 0),
i_dataIn => w_peripDataFromCPU,
o_dataOut => w_timerOut
);
Resources (EP4CE15)
- Logic Cells: 87
- Registers: 49
- Memory Bits: 0
