Extend IOP16 minimal example

Overview

This is a guide to extending the minimal IOP example by adding IOP16 Peripherals to the minimal design

• This is not the same as Embedding the IOP16 into another design
• This guide requires general familiarity with IOP16 16-bit I/O CPU Design
• This example does not cover porting to a different FPGA card
  • Will need to adjust I/O pin assignments if a different FPGA is used

Steps

• Start with baseline (minimal) design
• Copy/clone baseline (minimal) design
• Build baseline (minimal) design
• Copy design to new folder
• Select/add peripherals
• Create new peripherals
• Write assembly code
• Build/test

Baseline Design

Starts from IOP example

• Similar to Arduino "Blink Sketch" and uses the following resources
  • Timer Unit - 1 second timer
    • The Timer unit can be removed if not needed
    • Timer makes Blink easier
  • On-board LED

Copy/Clone Sources

• Clone the two repositories to the same directory level since relative paths are used for source files
  • IOP16 GitHub repository
  • Design a CPU GitHub repository
• Example copies files to TestBuild folder
• There are a lot of extra files in the two unzipped folders (380MB)

Alternately download ZIP files

• Alternately you can download the two ZIP files from GitHub

• Unzip these two folders into the same folder

• Rename the folders to remove the -main from the folder path

• Result

Build Minimal Design

Start by building the minimal example in Quartus II

• Open the Project file (TestIOP16B.qpf) in Quartus II
• Relative path: ..\TestBuild\IOP16\Higher_Level_Examples\TestIOP16_Minimal

• Entities in Quartus should look like

• Build FPGA (click the blue "Start Compilation arrow)

Fix ROM File Path

• Quartus does not verify the ROM file was correct
  • Could be buried in the status messages
  • Likely need to re-point to the ROM .MIF file since Quartus II sometimes "forgets"
  • Double click on the IOP_ROM file

• Hit finish
  • Check for error message

• Re-point to the ROM file
• Make sure to select .MIF file extension

Build Again / Download

• Build again
• Should be no error messages
• Result

• Download to FPGA
• Make sure pointing to the right folder

• User LED should be blinking

Copy Design to new folder

• Copy from folder ..\TestBuild\IOP16\Higher_Level_Examples\TestIOP16_Minimal

• Copy to folder ..\TestBuild\IOP16\Higher_Level_Examples\TestIOP16_UART_Loopback

• Build (as above)

• Make sure to update ROM file (as above)
• Make sure pointing to the right folder when downloading
• Test (as above)

Select Peripherals

• Pick from Supported peripherals list
• This example will add UART peripheral
  • Will set up UART in loopback

• Update Memory map in comments at start of TestIOP16B.vhd to add UART addresses

-- IOP16 MEMORY Map
-- 0X00      - KEY1 Pushbutton (R)
-- 0X00      - User LED (W)
-- 0x04-0x07 - Timer Unit
-- 0X08      - UART (Cmd/Stat) (r/w)
-- 0X09      - UART (Data) (r/w)

• Add UART files to project

• Select VHDL files from \TestBuild\Design_A_CPU\Peripherals\UART folder

• Add UART pins to top level entity pins list

entity TestIOP16B is
  port
  (
    -- Clock and Reset
    i_clk     : in std_logic := '1';		-- Clock (50 MHz)
    i_n_reset : in std_logic := '1';		-- SW2 on FPGA the card
    -- The key and LED on the FPGA card 
    i_key1    : in std_logic := '1';		-- SW1 on the FPGA card
    o_UsrLed  : out std_logic := '1';		-- USR LED on the FPGA card
		
    rxd1      : in std_logic := '1';		-- Hardware Handshake needed
    txd1      : out std_logic;
    cts1      : in std_logic := '1';
    rts1      : out std_logic;
    ...

• Add to signals list

-- Decodes/Strobes
signal w_wrUart				:	std_logic;
signal w_rdUart				:	std_logic;
signal w_UartDataOut			:	std_logic_vector(7 downto 0);
...
-- Interfaces
signal w_UartDataOut			:	std_logic_vector(7 downto 0);
...
-- Serial clock enable
signal serialEn      		: std_logic;		-- 16x baud rate clock

• Add UART instance to section after begin

-- 6850 style UART
UART: entity work.bufferedUART
  port map (
    clk     			=> i_CLOCK_50,
    -- Strobes
    n_wr				=> not w_wrUart,
    n_rd    			=> not w_rdUart,
    -- CPU 
    regSel  			=> w_periphAdr(0),
    dataIn  			=> w_periphOut,
    dataOut 			=> w_UartDataOut,
    -- Clock strobes
    rxClkEn 			=> serialEn,
    txClkEn 			=> serialEn,
   -- Serial I/F
    urxd     			=> urxd1,
    utxd     			=> utxd1,
    urts   			=> urts1,
    ucts   			=> ucts1
  );

• Add Baud Rate Generator instance

-- Baud Rate Generator
-- These clock enables are asserted for one period of input clk, at 16x the baud rate.
-- Set baud rate in BAUD_RATE generic
BAUDRATEGEN	:	ENTITY work.BaudRate6850
  GENERIC map (
    BAUD_RATE	=> 115200
  )
  PORT map (
  i_CLOCK_50	=> i_CLOCK_50,
  o_serialEn	=> serialEn
);

• Add Chip selects logic
• Make sure to set the address of the UART (0x08-0x09 in this instance)

-- Strobes/Selects
w_wrUart <= '1' when ((w_periphAdr(7 downto 1)="0000100") and (w_periphWr = '1')) else '0';
w_rdUart <= '1' when ((w_periphAdr(7 downto 1)="0000100") and (w_periphRd = '1')) else '0';

• Add UART output data to w_periphIn
• Make sure to set the address of the UART (0x08-0x09 in this instance)

-- Peripheral bus read mux
w_periphIn <=	"0000000"&w_keyBuff when w_periphAdr=x"00"							else
                w_timerOut          when w_periphAdr(7 downto 2) = "000001"	else
                w_UartDataOut       when w_periphAdr(7 downto 1) = "0000100"	else
                x"00";

• May have to fix some signal names
  • i_CLOCK_50 -> i_clk

Create new peripherals

• Patterned like above example
• Takes in signals w_periphAdr, w_periphOut, w_periphWr, w_periphRd
• Create out signal and add to mux
• Create needed signals
• Create strobes