Features
- Serial/Parallel I/O Card
- 68B50 UART
- 1.8432 MHz oscillator
- Baud Rate Clock (115,200 baud oscillator)
- Control PLD
- 100x50mm card
Design
ACIA
- 68B50 UART
- Baud Rate Clock (115,200 baud oscillator)
PLD
LB-68B50-02_6XXX_PLD Listing
- 6XXX (6502, 6802, 6809 specific)
Name LB-68B50-02_6XXX_PLD;
Partno ATF16V8B;
Date 09/20/24;
Revision 01;
Designer DOUG G;
Company LAND BOARDS LLC;
Assembly LB-68B50-02_6XXX_U2;
Location Rustbelt, US;
Device G16V8;
/*
68B50 Control for LB-6809-01, LB-6802-01, and LB-65CXX CPU boards
0x8000-0xBFFF - 16KB I/O space
*/
/* Control inputs */
PIN 1 = CPUA15;
PIN 2 = CPUA14;
PIN 3 = CPUA13;
PIN 4 = CPUA12;
PIN 5 = CPUA11;
PIN 6 = CPUA10;
PIN 7 = CPUA1;
PIN 8 = CPUA0;
PIN 9 = !IOCS; /* IOCS is IO space decoded on all CPU cards */
PIN 11 = VDA; /* Not used in any version */
PIN 12 = VPB; /* VPB is enable on 6802, 6809 AND 6502 (Rev 2 rwk) CPUs */
PIN 14 = !IORQ; /* IORQ* is enable on Z80 cards */
/* Address Decode and Chip Select outputs */
PIN 16 = ACIACS1;
PIN 17 = ACIACS0;
PIN 18 = ACIARS;
PIN 19 = ACIAE;
ACIACS1 = CPUA15 & !CPUA14 & IOCS;
ACIACS0 = CPUA15 & !CPUA14 & IOCS;
ACIARS = CPUA0;
ACIAE = CPUA15 & !CPUA14 & IOCS & VPB;
LB-68B50-02_Z80_PLD PLD Listing
Name LB-68B50-02_Z80_PLD;
Partno ATF16V8B;
Date 09/19/24;
Revision 01;
Designer DOUG G;
Company LAND BOARDS LLC;
Assembly LB-6850-02_U2;
Location Rustbelt, US;
Device G16V8;
/*
68B50 Control for Z80 CPU board
*/
/* Control inputs */
PIN 1 = CPUA15;
PIN 2 = CPUA14;
PIN 3 = CPUA13;
PIN 4 = CPUA12;
PIN 5 = CPUA11;
PIN 6 = CPUA10;
PIN 7 = CPUA1;
PIN 8 = CPUA0;
PIN 9 = !IOCS;
PIN 11 = VDA;
PIN 12 = VPB;
PIN 13 = !IORQ;
/* Address Decode and Chip Select outputs */
PIN 16 = ACIACS1;
PIN 17 = ACIACS0;
PIN 18 = ACIARS;
PIN 19 = ACIAE;
ACIACS1 = IOCS & IORQ;
ACIACS0 = IOCS & IORQ;
ACIARS = CPUA0;
ACIAE = IOCS & IORQ;
- GND
- CTS (in)
- VCC
- TX (out)
- RX (in)
- RTS (out)
Backplane
Mechanicals
Rev 2
Rev 1
Checkout
Rev 2 Changes
- Fixed IOCS* to be on J1-38
- Fixed IORQ signal
- Inv on one end but not on the other end on schematic
- Added config jumper J3 into PLD (U2-14) to allow for 2 configs
- Add LED with resistor to U2-15
Rev 1
- Missing IORQ signal. Inv on once end but not on other end
- Add wire U2-13 to J1-51 (Z80)
- IOCS* is on wrong pin (J1-37)
- IOCS* should be on pin (J1-38)
Mechanicals
Assembly Sheet
Rev 2
Rev 1