Difference between revisions of "Embed IOP16"

From Land Boards Wiki
Jump to navigation Jump to search
(Created page with "== Example Applications == * [https://hackaday.io/project/180415-ansi-terminal-in-an-fpga Hackaday ANSI Terminal in an FPGA] * [https://github.com/douggilliland/Design_A_CPU...")
 
Line 1: Line 1:
 +
== CPU Entity ==
 +
 +
* The CPU entity has the minimal connection needed to use the CPU in an embedded application
 +
* Copy/paste the CPU entity into the next higher-level VDHL file
 +
 +
<pre>
 +
--  IOP16 Peripheral bus
 +
signal w_periphAdr        : std_logic_vector(7 downto 0);
 +
signal w_peripDataToCPU  : std_logic_vector(7 downto 0);
 +
signal w_peripDataFromCPU : std_logic_vector(7 downto 0);
 +
signal w_periphWr        : std_logic;
 +
signal w_periphRd        : std_logic;
 +
 +
CPU : ENTITY work.cpu_001
 +
  generic map (
 +
    INST_ROM_SIZE_PASS => 512, -- Instruction ROM size
 +
    STACK_DEPTH_PASS  => 4    -- JSR/RTS nesting depth - Stack size 2^n - n (4-12 locations)
 +
  )
 +
PORT map
 +
(
 +
  i_clock            => i_clock,            -- 50 MHz clock
 +
  i_resetN          => w_resetClean_n,    -- Reset CPU active low
 +
  i_peripDataToCPU  => w_peripDataToCPU,  -- Data from the Peripherals to the CPU
 +
  -- Peripheral bus
 +
  o_peripAddr        => w_peripAddr,        -- Peripheral address bus (256 I/O locations)
 +
  o_peripDataFromCPU => w_peripDataFromCPU, -- Data from CPU to Peripherals
 +
  o_peripWr          => w_peripWr,          -- Write strobe
 +
  o_peripRd          => w_peripRd          -- Read strobe
 +
);
 +
 +
</pre>
 +
 +
=== CPU Entity  ===
 +
 +
* Two generics can be modified
 +
** INST_ROM_SIZE_PASS - Instruction ROM size
 +
*** Legal sizes are 512W, 1KW, 2KW, 4KW
 +
**** 512W uses 1 of 1K Blocks in EP4CE15 FPGA
 +
*** Should match ROM application size
 +
** STACK_DEPTH_PASS - JSR/RTS nesting depth - Stack size 2^n - n (4-12 locations)
 +
*** Legal sizes
 +
**** 0 - None
 +
**** 1 - Single deep - Doesn't need SRAM
 +
**** 2, 3, 4 - Needs SRAM
 +
 +
=== IOP16 CPU Resources ===
 +
 +
* Logic Cells: 271
 +
* Registers: 76
 +
* Memory bits: 8192 (512W)
 
== Example Applications ==
 
== Example Applications ==
  
 
* [https://hackaday.io/project/180415-ansi-terminal-in-an-fpga Hackaday ANSI Terminal in an FPGA]
 
* [https://hackaday.io/project/180415-ansi-terminal-in-an-fpga Hackaday ANSI Terminal in an FPGA]
 
* [https://github.com/douggilliland/Design_A_CPU Design a CPU] - GitHub
 
* [https://github.com/douggilliland/Design_A_CPU Design a CPU] - GitHub

Revision as of 09:48, 11 April 2022

CPU Entity

  • The CPU entity has the minimal connection needed to use the CPU in an embedded application
  • Copy/paste the CPU entity into the next higher-level VDHL file
--  IOP16 Peripheral bus
signal w_periphAdr        : std_logic_vector(7 downto 0);
signal w_peripDataToCPU   : std_logic_vector(7 downto 0);
signal w_peripDataFromCPU : std_logic_vector(7 downto 0);
signal w_periphWr         : std_logic;
signal w_periphRd         : std_logic;

CPU : ENTITY work.cpu_001
  generic map ( 
    INST_ROM_SIZE_PASS => 512, -- Instruction ROM size
    STACK_DEPTH_PASS   => 4    -- JSR/RTS nesting depth - Stack size 2^n - n (4-12 locations)
  )
PORT map 
(
  i_clock            => i_clock,            -- 50 MHz clock
  i_resetN           => w_resetClean_n,     -- Reset CPU active low
  i_peripDataToCPU   => w_peripDataToCPU,   -- Data from the Peripherals to the CPU
  -- Peripheral bus
  o_peripAddr        => w_peripAddr,        -- Peripheral address bus (256 I/O locations)
  o_peripDataFromCPU => w_peripDataFromCPU, -- Data from CPU to Peripherals
  o_peripWr          => w_peripWr,          -- Write strobe
  o_peripRd          => w_peripRd           -- Read strobe
);

CPU Entity

  • Two generics can be modified
    • INST_ROM_SIZE_PASS - Instruction ROM size
      • Legal sizes are 512W, 1KW, 2KW, 4KW
        • 512W uses 1 of 1K Blocks in EP4CE15 FPGA
      • Should match ROM application size
    • STACK_DEPTH_PASS - JSR/RTS nesting depth - Stack size 2^n - n (4-12 locations)
      • Legal sizes
        • 0 - None
        • 1 - Single deep - Doesn't need SRAM
        • 2, 3, 4 - Needs SRAM

IOP16 CPU Resources

  • Logic Cells: 271
  • Registers: 76
  • Memory bits: 8192 (512W)

Example Applications

Retrieved from "http://land-boards.com/blwiki/index.php?title=Embed_IOP16&oldid=13408"