Embed IOP16

CPU Entity

• The CPU entity has the minimal connection needed to use the CPU in an embedded application
• Copy/paste the CPU entity into the next higher-level VDHL file

--  IOP16 Peripheral bus
signal w_periphAdr        : std_logic_vector(7 downto 0);
signal w_peripDataToCPU   : std_logic_vector(7 downto 0);
signal w_peripDataFromCPU : std_logic_vector(7 downto 0);
signal w_periphWr         : std_logic;
signal w_periphRd         : std_logic;

CPU : ENTITY work.cpu_001
  generic map ( 
    INST_ROM_SIZE_PASS => 512, -- Instruction ROM size
    STACK_DEPTH_PASS   => 4    -- JSR/RTS nesting depth - Stack size 2^n - n (4-12 locations)
  )
PORT map 
(
  i_clock            => i_clock,            -- 50 MHz clock
  i_resetN           => w_resetClean_n,     -- Reset CPU active low
  i_peripDataToCPU   => w_peripDataToCPU,   -- Data from the Peripherals to the CPU
  -- Peripheral bus
  o_peripAddr        => w_peripAddr,        -- Peripheral address bus (256 I/O locations)
  o_peripDataFromCPU => w_peripDataFromCPU, -- Data from CPU to Peripherals
  o_peripWr          => w_peripWr,          -- Write strobe
  o_peripRd          => w_peripRd           -- Read strobe
);

CPU Entity

• Two generics can be modified
  • INST_ROM_SIZE_PASS - Instruction ROM size
    • Legal sizes are 512W, 1KW, 2KW, 4KW
      • 512W uses 1 of 1K Blocks in EP4CE15 FPGA
    • Should match ROM application size
  • STACK_DEPTH_PASS - JSR/RTS nesting depth - Stack size 2^n - n (4-12 locations)
    • Legal sizes
      • 0 - None
      • 1 - Single deep - Doesn't need SRAM
      • 2, 3, 4 - Needs SRAM

IOP16 CPU Resources

• Logic Cells: 271
• Registers: 76
• Memory bits: 8192 (512W)

Example Applications

• Hackaday ANSI Terminal in an FPGA
• Design a CPU - GitHub

Connect to High Level

• Peripheral elements are linked to the Peripheral address, data busses and strobes