Difference between revisions of "QTPy49"

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Line 9: Line 9:
 
** [https://www.seeedstudio.com/XIAO-RP2040-v1-0-p-5026.html Seeed XIAO RP2040]
 
** [https://www.seeedstudio.com/XIAO-RP2040-v1-0-p-5026.html Seeed XIAO RP2040]
 
* Socketed CPU
 
* Socketed CPU
* Connectors
+
* Headers
 
** DC Power
 
** DC Power
 
** AD0-AD3 GVS
 
** AD0-AD3 GVS

Revision as of 15:11, 4 June 2022

QTPy49 FRONT REV1.png

Features

Connectors

QTPy49 CAD.PNG

  • Ground, Voltage, Signal (GVS) connections

J1 - DC In

  • 7-12V
  • Center positive

J2 - Short Regulator

  • Install if J1 has 5V
  • No need to install U2 regulator

J3 - SPI

  1. GND
  2. 3.3V
  3. SS, AD3
  4. MOSI, S10
  5. MISO, D9
  6. SCK, D8

J4 - UART

  1. GND
  2. 3.3V
  3. TX, D6
  4. RX, D7

J5 - I2C

  1. GND
  2. 3.3V
  3. D4, SDA
  4. D5, SCL

J6 - AD3

  • Digital I/O 3
  • Analog In 3
  • PWM output
  • Capacitive touch input
  • Pinout
  1. GND
  2. 3.3V
  3. AD3

J7 - AD2

  • Digital I/O 2
  • Analog In 2
  • PWM
  • Capacitive touch input
  • Pinout
  1. GND
  2. 3.3V
  3. AD2

J8 - AD1

  • Digital I/O 1
  • Analog In 1
  • Capacitive touch input
  • AREF pin
  • Pinout
  1. GND
  2. 3.3V
  3. AD1

J9 - AD0

  • Digital I/O 0
  • Analog In 0
  • True analog output with 10 bit precision
  • Does not have PWM
  • Capacitive touch input
  • Pinout
  1. GND
  2. 3.3V
  3. AD0

Mechanicals

QTPy49 MECHS.PNG


Assembly Sheet