Difference between revisions of "R32V2020 32-bit RISC CPU Design"

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(Created page with "* 32-bit RISC CPU * [https://github.com/douggilliland/R32V2020 Land Boards R32V2020] * [https://github.com/douggilliland/R32V2020/tree/master/Assembler Land Boards R32V2020 As...")
 
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* [https://github.com/douggilliland/R32V2020/tree/master/Assembler Land Boards R32V2020 Assembler]
 
* [https://github.com/douggilliland/R32V2020/tree/master/Assembler Land Boards R32V2020 Assembler]
 
* [https://github.com/douggilliland/R32V2020/tree/master/Programs Land Boards Example code]
 
* [https://github.com/douggilliland/R32V2020/tree/master/Programs Land Boards Example code]
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= R32V2020 - 32-Bit RISC =
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* R32V2020 is a 32-bit RISC CPU.
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* R32V2020 runs at 12.5 MIPS with a 50 MHz clock (4 clocks per instruction).
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* R32V2020 is [[Why VHDL for the R32V2020|written in VHDL]].
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* R32V2020 is intended to be [[Target Hardware|implemented in an FPGA]].
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* R32V2020 is a '''non-'''[https://en.wikipedia.org/wiki/Von_Neumann_architecture Von Neumann architecture] so it may be unfamiliar at first glance.
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** Attempts to avoid the [https://web.archive.org/web/20131212205159/http://aws.linnbenton.edu/cs271c/markgrj/ Von Neumann bottleneck] by having a separate instruction memory space
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= Details =
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* [[Architecture]] - R32V2020 architecture.
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* [[Instruction Set]]
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** [https://github.com/douggilliland/R32V2020/blob/master/Assembler/R32V2020_Reference_Card.pdf Programmer's Reference Card]
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* [[Target Hardware]] - FPGA Resource Requirements
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** [[Resource requirements]]
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** [[Porting to other FPGAs|Porting R32V2020 to other FPGAs]].
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* [[Peripheral Interfaces]] - Peripheral IP that was developed under [http://searle.hostei.com/grant/Multicomp/index.html Multicomp project], [https://github.com/mvvproject/ReVerSE-U16 ReVerSE-16 project] and other projects.
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* [[Software Support]] - R32V2020 Software Support document(s).
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** [[Assembler]]
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** [[C Compiler]]
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* [[Adding an Instruction to the ISA]]
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* [[Performance]]
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* [[Micro-Code]]
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* [[Debug and Troubleshooting]]
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* [https://www.youtube.com/watch?v=YuXSBQsL4EQ&list=PLn__0BqzWEWPIsUE0TUdsspej2vHV-osY R32V2020 Video Playlist]
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= Ownership =
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* We all stand on the shoulders of giants.
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** Grant Searle's [http://searle.hostei.com/grant/Multicomp/index.html Multicomp project].
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** Neil Crook's [https://github.com/nealcrook/multicomp6809 improvements to Multicomp].
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* The concepts in this RISC design are found in any Computer Architecture Design textbook.
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* [http://www.fpgacpu.org/papers/soc-gr0040-slides.pdf Nice slideshow on another FPGA RISC design]
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= Warning =
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* No warranty expressed or implied.

Revision as of 11:37, 10 April 2022

R32V2020 - 32-Bit RISC

Details

Ownership

Warning

  • No warranty expressed or implied.
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