R32V2020 Instruction Space
Revision as of 11:49, 10 April 2022 by Blwikiadmin (talk | contribs) (Created page with "* All instructions are 32-bits ** Instruction code fields in consistent positions * Read-only from the CPU ** No self modifying code for security reasons ** Loadable via physi...")
- All instructions are 32-bits
- Instruction code fields in consistent positions
- Read-only from the CPU
- No self modifying code for security reasons
- Loadable via physical connection to FPGA via program loader
- 32-bit instruction Pointer address register
- Auto-increments after read
