Difference between revisions of "RETRO-65C816"
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[[file:TimingTable_65C816.PNG]] | [[file:TimingTable_65C816.PNG]] | ||
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| + | == Mechanicals== | ||
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| + | [[file:RETRO-65C816_MECHS_CAD.PNG]] | ||
== Assembly Sheet == | == Assembly Sheet == | ||
* [[RETRO-65C816 Rev 1 Assembly Sheet]] | * [[RETRO-65C816 Rev 1 Assembly Sheet]] | ||
Revision as of 01:13, 30 May 2022
Features
- 65C816 CPU
- 3.3V
- 8 MHz
- All pins are brought to FPGA
- Address A0-A15 and Data lines also go directly to the SRAM
- FPGA can have the ROM internally or download it to the SRAM
- 1MB SRAM
- 45nS access time
- USB B
- FTDI USB to TTL
- Tx/Rx LEDs
- VGA
- 2:2:2 R:G:B
- PS/2 keyboard
- 5V KEYBOARD
- Level translator to 3.3V for FPGA
- SD card socket
- Full-sized SD
- QMTECH FPGA card mounts on top
- 95x95mm card
- ODAS form factor
65C816 CPU
Block Diagram
Timing
Mechanicals
