SYNTH-MIDI-CTL-01

Features

• Adapted from HAGIWO's MIDI to CV module
  • Translate from Japanese to English using browser
• XAIO RP2040 CPU
  • Arduino MIDI library has not yet been ported to Pico so will need to use CircuitPython MIDI Library
• MIDI In/Out
  • Standard MIDI Jacks
  • MIDI out jack for future functionality
• (2) 0-5V Analog CV outs
  • MCP4822 12-bit D/A - SPI Interface
    • MCP4822 Datasheet
  • Use with SYNTH-VCO-01
    • CV1 = V/OCT
    • CV2 = MOD
• (2) Digital Outs, eX:
  • Gate
  • Clock
• Pot supports setting Clock rate
• Standard EuroRack 16 pin header
  • Supports 12V in with on-board 5V regulator
  • 5V regulator can be not installed if 5V is available on EuroRack connection
• Card is not a Eurorack card
  • Probably too deep, needs cabling
• (6) 6-32 Mounting holes
  • Stacks with SYNTH-VCO-01 card

RP2040 Pin Assignments

• Pins
  • A0, P26 = CLK_POT
  • D2 = SPI_SS
  • D3 = Gate (Out)
  • D4 = MIDI Clk (Out)
  • D5 = SPI_LDAC
  • D6/TX - MIDI_Out
  • D7/RX = MIDI In
  • D8 = SPI_SCK
  • D9 = Unused
  • D10 = MOSI

Connectors

J1 - Power

• Eurorack compatible pinout
• Fits a shrouded connector with some interference with Voltage Regulator U1

J5, J7 - Controle Voltages Out

• Chart from video

Videos

• Similar design

Software

• MIDI Messages
• HAGIWO 's code runs on an Arduino NANO and was developed in the Arduino IDE
• However, there's no Arduino MIDI library for the RP2040
• This is a port of Arduino code to CircuitPython done in pieces

HAGIWO code baseline

• SYNTHMIDICTL01.ino
  • Runs on Arduino NANO
  • Used as baseline and converted to CircuitPython

CircuitPython

• synth_midi_ctl_01_001.py
  • Toggles the GATE, CLK lines
• synth_midi_ctl_01_002.py
  • Blinks the GATE, CLK lines
  • MIDI over USB
  • Parses MIDI messages, print to REPL
  • Pick out single notes since SYNTH is monophonic

SPI Code

• Adafruit Learn SPI Tutorial

# imports
import board
import busio
import digitalio

# Set up Chip Select pin
cs = digitalio.DigitalInOut(board.D2)
cs.direction = digitalio.Direction.OUTPUT
cs.value = True

# Create an interface to the SPI hardware bus
spi = busio.SPI(board.SCK, MISO=board.MISO)

# Lock the bus

while not spi.try_lock():
    pass

# The busio.SPI.configure() function is called to configure the speed, phase, and polarity of the SPI bus. 
# It’s important to always call configure after locking the bus and before talking to your device as communication 
# with other devices might have changed the speed, polarity, etc.
# You’ll need to look up the exact speed and other values from your device’s datasheet. 
# For the MAX31855 (example) we’ll use a speed of 5mhz and a polarity and phase of 0 (sometimes called mode 0).

spi.configure(baudrate=5000000, phase=0, polarity=0)
cs.value = False

# Read example (not used)
result = bytearray(4)
spi.readinto(result)
cs.value = True
# result
# bytearray(b'\x01\xa8\x1a\xf0')

# Write example
spi.configure(baudrate=5000000, phase=0, polarity=0)
cs.value = False
spi.write(bytes([0x01, 0xFF]))
cs.value = True

# Need to unlock bus when done
spi.unlock()

Issues

Rev 2

• Moved U4 down a bit
• Add 0.1uF cap MIDI In pin 2 to GND
• Double inverted clocks
  • Rev 1 had single inversion
• Will be software difference to invert/not invert clocks
• Moved MIDI In off 74HC14 since it is 5V out on 74HC14

Rev 1 Checkout

• D9 s/b 1N914
• s/s R1 has 1K, P/L has 2.7K
• R1 pullup could be moved to Vcc (+5V)
• DIN-5 J4 could use a 0.1uF cap to logic ground
• J1 fits with a shrouded connector has some interference with Voltage Regulator U1
• U4 is connected to 5V power but drives into XIAO - needs to be clamped to 3.3V
• Cut trace U4-10 (RXD) front side
• Add wire U4-13 to U2-8 (RXD)

Assembly Sheet

• SYNTH-MIDI-CTL-01 Rev 1 Assembly Sheet