Difference between revisions of "IOP16 16-bit I/O CPU Design"

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* [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15/M6800_MIKBUG_FrontPanel01 6800 CPU with Front Panel]
 
* [https://github.com/douggilliland/MultiComp/tree/master/MultiComp_On_RETRO-EP4CE15/M6800_MIKBUG_FrontPanel01 6800 CPU with Front Panel]
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* [[Front Panel for 8 Bit Computers V2]]
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=== Front Panel Loopback ===
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* [https://github.com/douggilliland/IOP16/tree/main/Higher_Level_Examples/Front%20Panel%20Examples/FrontPanel01_Test_LoopBack Front Panel Loopback FPGA]
 
* [https://github.com/douggilliland/IOP16/tree/main/Higher_Level_Examples/Front%20Panel%20Examples/FrontPanel01_Test_LoopBack Front Panel Loopback FPGA]
 
* [https://github.com/douggilliland/Design_A_CPU/tree/main/CPU_Code/Application_Code/FP01_LOOP4 Front Panel Loopback Code]
 
* [https://github.com/douggilliland/Design_A_CPU/tree/main/CPU_Code/Application_Code/FP01_LOOP4 Front Panel Loopback Code]

Latest revision as of 17:45, 19 April 2022

Overview

This CPU is intended to be used as an I/O Processor. The CPU can be used as a Microcontroller replacement in many applications. It can be embedded into an FPGA with a separate Host Computer off-loading tedious I/O programming. It is useful for offloading polled I/O or replacing CPUs in small applications. The majority of these applications deal with 8-bit data and that's where this CPU excels.

Video PlayList

Features Set

  • 16-bit CPU
  • Simple/consistent opcode bit fields
    • Instructions are always 16-bits wide
    • 4-bit opcode
      • Some "sub-instructions" allow more than 16 instructions
    • 4-bit register field (shared with address/offset)
    • 8-bit constant (shared with address/offset)
  • High enough IOP-16 Performance - 12.5 MIPS
    • 4 of 50 MHz FPGA clocks
  • Register File
    • 4, 8, or 13 General Purpose registers
    • 3 constant value registers
    • Registers are 8-bits
  • 12-bit of Program address (up to 4K instructions)
  • IOP-16 Stack
    • 0 (none)
    • 1 deep
    • Optionally deeper as build option (uses SRAM)

IOP16 Block Diagram

IOP16 Block-Diagram.png

Instruction Set

Assembler

  • Table driven Assembler
    • Input comes from a CSV file
    • Outputs .MIF and Listing files
      • MIF (Memory Initialization File) is Altera ROM initialization File

Hardware Requirements

  • Targeted at an FPGA implementation
    • The CPU could easily be run on pretty much any FPGA
    • Coded in VHDL

Resources

  • Very small LUT/Memory footprint in FPGA
  • Uses 271 logic cells in an Altera EP4 FPGA
  • Uses 76 registers in an Altera EP4 FPGA
  • Requires a minimum 1 of 1K SRAM blocks (depends on program size)
      • Trade-off - SRAM could be replaced with logic cells (in theory)

Target Hardware

CycloneIV Starter Kit P528-720px.jpg

Build on Cyclone 10 FPGA

Build into MultiComp in a Box

Peripheral Support

  • Extensive Peripheral Support
  • 8-bit address (controls up to 256 peripherals)
  • 8-bit data
  • Read strobe (a couple of clocks wide)
  • Write strobe (a couple of clocks wide)

Code Examples

Here are some Code and FPGA build example applications

Blink LED

Almost minimal design = CPU + Timer + LED

ANSI Terminal

6800 Microprocessor Front Panel

Front Panel Loopback

IOP16 Extending/Embedding Guide

External References