Front Panel for 8 Bit Computers V2

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FrontPanel02 P527-cropped-720px.jpg

Front Panel for 8-Bit Microprocessors v2

See here for Ver 1 - SMT version


This is a through-hole version of Front Panel for 8_Bit Computers.

It has these features. They may not fit your generic design. Especially since this card has to have an I2C interface.

  • 32 Pushbutton Switches
  • 32 LEDs
  • I2C interface (Two Wire interface - plus power and ground)
    • Jumper selectable base address
    • Occupies I2C addresses either 0x20-0x23 or 0x24-0x27
    • Jumper Selectable I2C terminators
  • I2C daisy-chain connector
    • Interrupt line
      • Can be configured to interrupt on button presses
      • MCP23017 need to be set to Open-Drain output - card has pull-up to Vcc
  • 4 of MCP23017 16-bit I2C Port Expanders
    • MCP23017 Datasheet - Rev D
    • MCP23017... LOST TWO INPUTS
      • MCP23017 now a 14/16-bit expander, with two of the pins (GPA7 and GPB7) losing their input capabilities
      • The chips look the same, are called the same, and act mostly the same — if you don’t download the latest version of the datasheet (Revision D), you’d never know that there’s been a change
    • These are fine pitch surface mount parts
  • 3.3V or 5V operation
  • Compatible form factor with RETRO-EP4CE15 and other cards
    • 95x95mm
    • 6-32 mounting holes


J2 - I2C Connector

  • Two row header on bottom of card
  • 5 pin in
  • 4 pin out (daisy-chain)
  1. GND
  2. VCC
  3. SDA
  4. SCL
  5. INT*


  1. GND
  2. VCC
  3. SDA
  4. SCL




  • D0-D7 - Data bus
  • A0-A15 - Address bus
  • Controls

Top row controls

Board has typical control silkscreen markings. It is all through hole so that it is much easier to assemble.


  • RUN - Run/Halt pushbutton, RUN LED on for CPU running
  • RESET - Reset the CPU
  • STEP - Single Step the CPU
  • Undefined
  • CLEAR - Clear address bus (if SETADR is ON) or data bus lines (if SETDAT is ON)
  • INCADR - Increment the address
    • If SETDAT is on write data
  • SETDAT - Set the data value
  • SETADR - Set the address


VHDL Driver

VHDL Entities

  • Panel Entity
-- -------------------------------------------------------------------------------------------------------
-- Front Panel starts here
-- Pass IOP16 code size and stack size down to the Front Panel
fp01 : work.FrontPanel01
	generic	map ( 
		INST_ROM_SIZE_IN	=> 512,			-- 512W code size
		STACK_DEPTH_IN		=> 4			-- 16 deep stack size
	port map
		-- Clock and reset
		i_CLOCK_50		=> i_CLOCK_50,		-- Clock (50 MHz)
		i_n_reset		=> i_n_reset,		-- Reset (from FGPGA KEY)
		-- 32 outs, 32 ins
		i_FPLEDs		=> w_LEDsOut,		-- Out to LEDs (32)
		o_PBRaw			=> w_PBsRaw,		-- Raw version of the  Pushbuttons (32)
		o_PBLatched		=> w_PBLatched,		-- Latched version of the  Pushbuttons (32)
		o_PBToggled		=> w_PBsToggled,	-- Toggle version of the  Pushbuttons (32)
		-- I2C interface
		io_I2C_SCL		=> io_I2C_SCL,		-- I2C clock to Front Panel card
		io_I2C_SDA		=> io_I2C_SDA,		-- I2C data to/from Front Panel card
		i_I2C_INTn		=> i_I2C_INTn		-- Interrupt input - active low

-- Front Panel ends here
-- -------------------------------------------------------------------------------------------------------
  • Higher level entity
    • 6800 with front Panel application
-- Front Panel
	port map
	-- Clock and reset
	i_CLOCK_50	=> i_CLOCK_50,
	i_cpuClock	=> w_cpuClock,
	i_n_reset	=> w_resetLow,
	o_FPReset	=> w_FPReset,
	-- CPU intercepts
	-- Front Panel loops back signals when in Front Panel switch is in Run Mode
	i_CPUAddress	=> w_cpuAddressB,
	o_CPUAddress	=> w_cpuAddress,
	i_cpuData	=> w_cpuDataOutB,
	o_cpuData	=> w_cpuDataOut,
	i_CPURdData	=> w_cpuDataIn,
	io_run0Halt1	=> w_run0Halt1,
	o_wrRamStr	=> w_wrRamStr,
	i_R1W0		=> w_R1W0B,
	o_R1W0		=> w_R1W0,
	-- External I2C connections
	io_I2C_SCL	=> io_I2C_SCL,
	io_I2C_SDA	=> io_I2C_SDA,
	i_I2C_INTn	=> i_I2C_INTn

6800 with Front Panel Operation

  • Memory map for this configuration is
0x0000-0x7FFF - 32KB INTERNAL SRAM
0xFC18-0xFC19 - VDU (serSelect J3 JUMPER REMOVED)
0xFC28-0xFC19 - ACIA
0xFC30-0xFC3F - Front Panel
0xF000-0xFFFF - MIKBUG ROM - Copied 4X


Halt CPU
  • Card comes up running SMITHBUG at 0xF000
  • RUN LED comes up on
  • A0-A15 LEDs light "dimly" once CPU is running
  • Other control LEDs off
  • Press RUN SW32 to halt CPU, LED will go off
  • A0-A31, D0-D7 LEDs may be off if run first time
    • May come up at address 0x0000 and show value in SRAM at that address (0x00 at power on)
Read from Program ROM
  • Enter address set mode by pressing SW24 SETADR pushbutton, LED will illuminate
  • Set address to 0xF000 by pressing A31, A30, A29, A28 LEDs will light
  • Press SETADR pushbutton again to exit set address mode, LED will go off
  • For MIKBUG, data will be 0x8E
  • Press INCADR SW26
  • Address will increment to 0F001
  • Data will show 0x7F
  • Next INCADR values are as follows
   f000   8e ef 44      LDS #STACK
   f003   bf ef 0a      STS SP
   f006   7f ef 0d      CLR ECHO	; DGG - default to serial port echo on
   f009   ce f1 25      LDX #SFE	; DGG - VECTORED SWI ROUTINE
   f00c   ff ef 17      STX SWIPTR
   f00f   ff ef 08      STX NIO
Access SRAM
  • Enter address set mode by pressing SW24 SETADR pushbutton, LED will illuminate
  • Set address to 0x0000
  • Press SETADR pushbutton again to exit set address mode, LED will go off
  • Press INCADR pushbutton to read data
  • Press SETDAT pushbutton to enter write data mode
  • Set the data value to write to SRAM on pushbuttons
  • Press INCADR to do the write and advance the address
  • Press SETDAT pushbutton again to exit write data mode
  • Verify data as above

Arduino Driver


PSoC Control

  • Z80 example

C Code

Assembly Sheet

Front Panel V2 Assembly Sheet Rev 1