Difference between revisions of "IOP-16 Performance"
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| + | * FPGA clock = 50 MHz | ||
* High enough IOP-16 Performance - 12.5 MIPS | * High enough IOP-16 Performance - 12.5 MIPS | ||
| − | * 4 of 50 MHz FPGA clocks | + | ** 4 of 50 MHz FPGA clocks |
== Peripheral Strobes == | == Peripheral Strobes == | ||
Revision as of 15:50, 19 April 2022
- FPGA clock = 50 MHz
- High enough IOP-16 Performance - 12.5 MIPS
- 4 of 50 MHz FPGA clocks
Peripheral Strobes
- 1 clock wide write strobes
- 2 clock wide read strobes
