IOP-16 Performance
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"Good enough" performance
- FPGA clock = 50 MHz
- High enough IOP-16 Performance - 12.5 MIPS
- 4 of 50 MHz FPGA clocks
- 80 nS instruction time
- 2-bit Grey-code counter
- Glitch-free operation
- 4 of 50 MHz FPGA clocks
Peripheral Strobes
- 1 clock wide write strobes
- 2 clock wide read strobes
