Difference between revisions of "EP2C5-DB"

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This is the EP4 version of the card.
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[[File:tindie-larges-v2.png|link=https://www.tindie.com/products/land_boards/z80-6502-6809-fpga-multicomp-pcb/]]
  

Revision as of 04:12, 8 October 2019

This is the EP4 version of the card.

Tindie-larges-v2.png

EP2CS-DB-170-X4-CCA-720px.jpg

Multi-Computer EP2C5 Daughtercard

This is a Cyclone II EP2C5 Mini Development Board daughtercard for Grant Searle's Multi-Computer design. Features:

  • EP2C5 FPGA board mounts below the card
    • Used standoffs to raise the Daughtercard
  • SRAM
  • Two Serial ports (connect to external FTDI or TTL-to-RS-232 converter cards)
  • SD Card (not MicroSD)
  • PS/2 keyboard connector
    • Needs to be able to run at 3.3V (not all keyboards can run at 3.3V)
  • Monochrome Composite Video Output (for UK101 6502 based project)
  • VGA connector (for M6809 or Z80 projects)
    • 6-bits of color (16-colors)
  • 5V power

My Retro Computer page

Features (from Grant's page)

  • Supports full features set of Grant's design
    • 6502, 6809 or Z80 processor running at up to 25MHz
    • Microsoft BASIC in ROM (copyright of the original respectfully acknowledged)
    • Serial ports (can support several) up to 115200 baud
    • PC monitor or TV (PAL/NTSC) with fully configurable 40x25, 80x25, 68x30 (or many other formats) monochrome or 16 colour display.
    • Character sizes also configurable.
    • Standard ANSI interpreter built-in to control cursor and colours.
    • PS2 (standard PC keyboard with round plug) keyboard with LED support.
    • SD card interface for CP/M or other use (simple interface for use within BASIC or machine code).
  • Daughtercard has the following support features
    • Mounts to the top of the EP2C5 FPGA card
      • Does not interfere with the FPGA pinouts
    • VGA and Composite video output connectors
    • Two Serial connectors
    • P/S Connector
    • External expansion SRAM
    • MicroSD card connections
    • Expansion connector with 8 additional connections

Grant's Announcement

"I have re-tested it today with the following computer builds, all working. 
These are just a FEW examples of the builds that you can do with the code that I have provided...

NO ADDITIONAL CHIPS (ALL INTERNAL TO THE FPGA)
6502 processor, 2K internal RAM, 40x25 full colour on a PAL monitor, PS2 keyboard
6809 processor, 2K internal RAM, 40x25 full colour on a PAL monitor, PS2 keyboard
6502 processor, 1K internal RAM, 40x25 full colour on a PAL monitor, PS2 keyboard
Z80 processor, 2K internal RAM, 40x25 full colour on a PAL monitor, PS2 keyboard
Z80 processor, 1K internal RAM, 40x25 full colour on a PAL monitor, PS2 keyboard
Z80 processor, 4K internal RAM, serial interface for I/O at 115200 baud
Z80 processor, 2K internal SRAM, 40x25 VGA monitor full colour display, PS2 keyboard

ONE ADDITIONAL SRAM CHIP
6502 processor, 8K external SRAM, 80x25 VGA monitor full colour display, PS2 keyboard
6502 processor, 32K external SRAM, 80x25 VGA monitor full colour display, PS2 keyboard
Z80 processor, 32K external SRAM, 80x25 VGA monitor full colour display, PS2 keyboard"

Other Pages

Connectors

EP2C5-DB-RevX4-Layout.PNG

P1-P4 - Connections to FPGA board

  • These are 2x14 pin 0.1" pitch female connectors which mount facing to the rear side of the card
  • The pinouts match the card pinouts

EP2C5-Mini-Board-TopView-512px.jpg

J1 - VGA

  • Standard VGA pinout

Vga pinout.JPG

J2 - Composite Video Output

  • RCA Connector
  • Center - video
  • Ring/shell - ground

J3 - P/S Keyboard Connector

  • 0.1" 1x6 right angle header
  1. GND
  2. VCC
  3. KBCLK
  4. KBDAT

PS/2 Keyboard Connector

PS2Conn.png

  • Pinout matches the DIN pinout but board does not support a DIN connection since this would most likely be a cable to a chassis mount connector
  • Bought this one on ebay
  • Note this board does not match the 5-pin header on the ebay cable since the pinout was unknown at the time this board was designed
  • Ebay colors (your may vary)
  1. GND = Orange
  2. VCC = Red
  3. CLK = Black
  4. DATA = Brown

UK101/Superboard Keyboard Mapping

opkbd.jpg

PS/2 Timing

J4 SD Connector

  • SD connector
  • Multicomp code does not support SDHC Cards
  • Neil Crook's 6809 code does support SDHC Cards

SD pinout.JPG

J5 - Serial #1/2

  • TTL Level Serial Ports
  • Connect to FTDI via 4:6 pin adapter cable
  • 2x4, 0.1" pitch connector
  • Pinout
  1. CTS-1
  2. CTS-2
  3. TX-1
  4. TX-2
  5. RX-1
  6. RX-2
  7. GND-1
  8. GND-2

FTDI Adapter cable

EP2C5-DB-FTDI-512px.jpg

J5 Pin J5 Description FTDI Pin FTDI Description
1,2 RTS 2 CTS
3,4 RXD 4 TXD
5,6 TXD 5 RXD
7,8 GND 1 GND

J6 - Expansion Connector

  • 2x6 0.1" pitch connector
  • Pinout
  1. VCC
  2. VCC
  3. P25
  4. P31
  5. P41
  6. P40
  7. P43
  8. P42
  9. P45
  10. P44
  11. GND
  12. GND

J8 - Expansion Connector

  • 2x6 0.1" pitch connector
  • Pinout
  1. VCC
  2. VCC
  3. P48
  4. P47
  5. P52
  6. P51
  7. P58
  8. P55
  9. P76
  10. P60
  11. GND
  12. GND

Hardware Checkout

  • P3-25 goes to reset switch not ground

Video Timing

PAL Searle timing NTSC timing
Osc freq 50000000 Hz Osc freq 50000000 Hz
Osc freq 50 MHz Osc freq 50 MHz
Osc period 2E-08 secs Osc period 2E-08 secs
Time per line 6.40E-05 uS Time per line 6.35E-05 uS
clocks per line 3200 clocks clocks per line 3175 clocks
Horiz Freq 15.6 KHz Horiz Freq 15.7 KHz
Horiz active 5.20E-05 secs Horiz active 5.26E-05 secs
Horiz active 2600 clocks Horiz active 2630 clocks
Horiz blank 1.2E-05 secs Horiz blank 1.09E-05 secs
Horiz blank 600 clocks Horiz blank 545 clocks
Horiz sync 4.70E-06 secs Horiz sync 4.70E-06 secs
Horiz sync 2.35E+02 clocks Horiz sync 2.35E+02 clocks
Front porch 8E-07 secs Front porch 1.50E-06 secs
Front porch 40 clocks Front porch 75 clocks
Back porch 4E-06 secs Back porch 4.70E-06 secs
Back porch 200 clocks Back porch 235 clocks
Total Blank 1.20E-05 secs Total Blank 1.09E-05 check number
Total Blank 600 clocks Total Blank 545 clocks
Vertical freq (goal) 50 Hz Vertical freq (goal) 59.94 Hz
Vertical time 0.02 secs Vertical time 0.016683350016683 secs
Vertical lines (calc) 312.5 lines Vertical lines (calc) 262.729921522572 lines
Vertical lines (round) 312 lines Vertical lines (round) 262 lines
Vert front porch 0 lines Vert front porch 0 lines
Vert sync 5 lines Vert sync 5 lines
Vert act start count 38 lines Vert act start count 6 lines
Vert active 255 lines Vert active 255 lines
Vert act end count 293 lines Vert act end count 261 lines
Vert back porch 19 lines Vert back porch 1 lines
Vert active check 256 lines Vert active check 256 lines
Vert blanking 57 lines Vert blanking 6 lines

Timing Waveforms - NTSC

Horizontal Timing

EP2C5-DB-1-Horiz-Timing.png

Horizontal Front Porch Timing

EP2C5-DB-6-Horiz-FP-Timing.png

Horizontal Sync Timing

EP2C5-DB-7-Horiz-Sync-Timing.png

Horizontal Back Porch Timing

EP2C5-DB-8-Horiz-BP-Timing.png

VHDL Code

Modified to run with an NTSC 60 Hz TV

library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	use ieee.std_logic_unsigned.all;

entity UK101TextDisplay is
	port (
		charAddr : out std_LOGIC_VECTOR(10 downto 0);
		charData : in std_LOGIC_VECTOR(7 downto 0);
		dispAddr : out std_LOGIC_VECTOR(9 downto 0);
		dispData : in std_LOGIC_VECTOR(7 downto 0);
		clk    	: in  std_logic;
		video		: out std_logic;
		sync  	: out  std_logic
   );
end UK101TextDisplay;

architecture rtl of UK101TextDisplay is

	signal hSync   : std_logic := '1';
	signal vSync   : std_logic := '1';

	signal vActive   : std_logic := '0';
	signal hActive   : std_logic := '0';

	signal	pixelClockCount: STD_LOGIC_VECTOR(3 DOWNTO 0); 
	signal	pixelCount: STD_LOGIC_VECTOR(2 DOWNTO 0); 
	
	signal	horizCount: STD_LOGIC_VECTOR(11 DOWNTO 0); 
	signal	vertLineCount: STD_LOGIC_VECTOR(8 DOWNTO 0); 

	signal	charVert: STD_LOGIC_VECTOR(3 DOWNTO 0); 
	signal	charScanLine: STD_LOGIC_VECTOR(3 DOWNTO 0); 

	signal	charHoriz: STD_LOGIC_VECTOR(5 DOWNTO 0); 
	signal	charBit: STD_LOGIC_VECTOR(3 DOWNTO 0); 

begin

	sync <= hSync and vSync;
	
	dispAddr <= charVert & charHoriz;
	charAddr <= dispData & charScanLine(3 DOWNTO 1);
	
	PROCESS (clk)
	BEGIN
	
-- UK101 display...
-- 64 bytes per line (48 chars displayed)	
-- 16 lines of characters
-- 8x8 per char

-- PAL timing
-- 64uS per horiz line (3200 clocks)
-- 4.7us horiz sync (235 clocks)
-- 5 lines vsync
-- 30 lines to start of display
-- 313 lines per frame
--
-- NTSC timing
-- 63.5uS per horiz line = 15.7 KHz horizontal timing = (3175 clocks)
-- 
-- 

		if rising_edge(clk) then
--			if horizCount < 3200 THEN -- PAL
			if horizCount < 3175 THEN -- NTSC
				horizCount <= horizCount + 1;
				if (horizCount < 40) or (horizCount > 3000) then
					hActive <= '0';
					pixelClockCount <= (others => '0');
					charHoriz <= (others => '0');
				else
					hActive <= '1';
				end if;

			else
				horizCount<= (others => '0');
				pixelCount<= (others => '0');
				charHoriz<= (others => '0');
--				if vertLineCount > 312 then  -- PAL
				if vertLineCount > 262 then
					vertLineCount <= (others => '0');
				else
--					if vertLineCount < 38 or vertLineCount > 293 then	-- PAL
					if vertLineCount < 6 or vertLineCount > 261 then
						vActive <= '0';
						charVert <= (others => '0');
						charScanLine <= (others => '0');
					else
						vActive <= '1';
--						if charScanLine = 15 then
						if charScanLine = 14 then
							charScanLine <= (others => '0');
							charVert <= charVert+1;
						else
--							if vertLineCount /= 38 then	-- PAL
							if vertLineCount /= 6 then
								charScanLine <= charScanLine+1;
							end if;
						end if;
					end if;

					vertLineCount <=vertLineCount+1;
				end if;

			END IF;
--			if horizCount < 235 then 	-- PAL
			if horizCount < 235 then	-- NTSC
				hSync <= '0';
			else
				hSync <= '1';
			end if;
			if vertLineCount < 5 then
				vSync <= '0';
			else
				vSync <= '1';
			end if;
			
			if hActive='1' and vActive = '1' then
				if pixelClockCount <5 then
					pixelClockCount <= pixelClockCount+1;
				else
					video <= charData(7-to_integer(unsigned(pixelCount)));
					pixelClockCount <= (others => '0');
					if pixelCount = 7 then
						charHoriz <= charHoriz+1;
					end if;
					pixelCount <= pixelCount+1;
				end if;
			else
				video <= '0';
			end if;
		end if;
	END PROCESS;	
  
 end rtl;

UK101 - Rev X1 PCB Checkout Pics

UK101

UK101-P1010540-720px.jpg

CEGMON w 4K RAM

UK101-CEGMON-P1010531-720px.JPG

Hello World

UK101-HelloWorld-P529-557px.jpg

Keyboard

UK101-Keyboard-P536-720px.JPG

CEGMON w External 41K RAM

UK101-P1010532-512pxV.jpg

VGA VHDL Code

  • All displays have similar timing relationship just with different timing numbers.
  • This code could replace the design code with something that is probably better formed.
  • VGA VHDL Code

Programming

Temporary Programming

Plug USB Blaster into JTAG connector

Program-temporarily-720px.PNG

Permanent Programming

Plug USB Blaster into AS (Active Serial) connector

Program-permanent-720px.PNG

Mapping the EP2C5-DB to the BASE-EP4CE6 board

Links

X4 Checkout

  • LED DS1 Silkscreen is backwards
  • A16 is on FPGA pin 32

X3 Checkout

SRAM Address Space Increase From 64K to 128K

  • SRAM A16 line (U1-2) was attached to GND in board Revs X1, X2
  • SRAM A16 line (U1-2) is connected to FPGA P22 pin/node in board Rev X1
  • Change requires an FPGA code change which will allow Neil Crook's MMU to be used
    • Problem: FPGA P22 is predefined as a clock input
      • Not sure why this is brought to a pin and not shown as predefined on the part
      • This could be cause of intermittent running of the CP/M code

Rework for SRAM Address change

  • Cut etch from P4-13 (FPGA P22) to U1-2 (Cut on Solder Side near U1-1)
  • Add wire on Solder Side of PCB from J7-5 (FPGA P32) to via that goes to U1-23

X2 Checkout

  • SD Card works although the driver does not work with SDHC cards so need regular SD Card (1 GB or 2 GB)
  • Having a off and on again problem with uploading to GitHub
    • Have had some intermittent success with typing the following into the Git Shell and then trying in the Windows Git
git config --global http.postBuffer 15728640

X2 Checkout Issues

  • "Rev X1" on rear silkscreen - use PTL to cover
  • VGA supports holes in wrong place - removed pins from conn
  • Should have 4 mounting holes to be more easily compatible with the ODAS
    • Should move memory down and add mtg hole in upper-left
  • Some of the EXPx pins are used already on the base board
    • J7 (EXP1) pins 17 and 27 are pre-defined on the FPGA board so it can't be used without modifications to the FPGA card
      • Pin 17 - 50MHz clock (output from oscillator on FPGA board, input to FPGA)
      • Pin 27 - Connected to GND. The "zero ohm" resistor could be removed and the pin used as normal.
    • J8 (EXP 3) pins 80 and 81 are pre-defined on the FPGA board so it can't be used without modifications to the FPGA card
      • Pin 80 - Connected to GND. The "zero ohm" resistor could be removed and the pin used as normal.
      • Pin 81 - Connected to Vcc 1.2V. The "zero ohm" resistor could be removed and the pin used as normal.
    • Move pins to all unused pins
  • Add an LED

X1 Checkout Issues

UK101-P1010539-720px.jpg

  • VGA pin spacing
  • Should be SD card not TF card spacing due to low density requirement (1GB or 2GB not SDHC)

Assembly Sheet / Parts List