Difference between revisions of "IOP-16 Performance"

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"Good enough" performance
+
= "Good enough" performance =
  
 
* FPGA clock = 50 MHz
 
* FPGA clock = 50 MHz
 
* High enough IOP-16 Performance - 12.5 MIPS
 
* High enough IOP-16 Performance - 12.5 MIPS
 
** 4 of 50 MHz FPGA clocks
 
** 4 of 50 MHz FPGA clocks
 +
*** 80 nS instruction time
 
** 2-bit [https://github.com/douggilliland/IOP16/blob/main/IOP16_CPU/GreyCode.vhd Grey-code counter]
 
** 2-bit [https://github.com/douggilliland/IOP16/blob/main/IOP16_CPU/GreyCode.vhd Grey-code counter]
 
*** Glitch-free operation
 
*** Glitch-free operation
  
== Peripheral Strobes ==
+
= Peripheral Strobes =
  
 
* 1 clock wide write strobes
 
* 1 clock wide write strobes
 
* 2 clock wide read strobes
 
* 2 clock wide read strobes

Latest revision as of 15:56, 19 April 2022

"Good enough" performance

  • FPGA clock = 50 MHz
  • High enough IOP-16 Performance - 12.5 MIPS
    • 4 of 50 MHz FPGA clocks
      • 80 nS instruction time
    • 2-bit Grey-code counter
      • Glitch-free operation

Peripheral Strobes

  • 1 clock wide write strobes
  • 2 clock wide read strobes